SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 33

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 11.
Table 12.
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 24
23 to 20
19 to 17
16
15 to 12
11 to 8
7
6 to 5
4
3 to 0
For details on register bit description, refer to
Symbol
-
DPN[3:0]
-
P_INDICATOR
N_CC[3:0]
N_PCC[3:0]
PRR
-
PPC
N_PORTS[3:0]
HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation
HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit description
8.1.3 HCSPARAMS register
PRR
31
23
15
R
R
R
R
0
0
0
7
0
The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that
are structural parameters. The bit allocation is given in
Description
reserved; write logic 0
Debug Port Number: This field identifies which of the host controller ports is the debug port.
reserved; write logic 0
Port Indicators: This bit indicates whether the ports support port indicator control.
Number of Companion Controller: This field indicates the number of companion controllers
associated with this Hi-Speed USB host controller.
Number of Ports per Companion Controller: This field indicates the number of ports
supported per companion host controller.
Port Routing Rules: This field indicates the method used to map ports to companion
controllers.
reserved; write logic 0
Port Power Control: This field indicates whether the host controller implementation includes
port power control.
N_Ports: This field specifies the number of physical downstream ports implemented on this
host controller.
30
22
14
R
R
R
R
0
0
0
6
0
N_CC[3:0]
DPN[3:0]
reserved
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev.
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 01 — 18 November 2009
PPC
28
20
12
R
R
R
R
0
0
0
4
1
reserved
27
19
11
R
R
R
R
0
0
0
3
0
reserved
Table
26
18
10
R
R
R
R
0
0
0
2
N_PORTS[3:0]
0
Hi-Speed USB OTG controller
N_PCC[3:0]
11.
25
17
R
R
R
R
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
P_INDICAT
OR
33 of 166
24
16
R
R
R
R
0
0
8
0
0
1
1.0”.