SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 93

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 85.
[1]
SAF1761_1
Product data sheet
Bit
7
6
5
4
3
2
1
0
[1]
To use port 1 as a host controller, write 0080 0018h to this register after power-on. To use port 1 as a peripheral controller, write
0006 0400h to this register after power-on.
Symbol
SW_SEL_HC
_
DC
VBUS_CHRG Connect V
VBUS_
DISCHRG
VBUS_DRV
SEL_CP_EXT 0 — Internal charge pump selected
DM_
PULLDOWN
DP_
PULLDOWN
DP_PULLUP
OTG Control register (address set: 0374h, clear: 0376h) bit description
Description
In software HNP mode, this bit selects between the host controller and the peripheral controller.
0 — Host controller connected to ATX
1 — Peripheral controller connected to ATX
This bit is set to logic 1 by hardware when there is an event corresponding to the BDIS_ACON
interrupt. BDIS_ACON_EN is set and there is an automatic pull-up connection on remote
disconnect.
Discharge V
Drive V
1 — External charge pump selected
DM pull-down:
0 — Disable
1 — Enable
DP pull-down:
0 — Disable
1 — Enable
0 — The pull-up resistor is disconnected from the DP line. The data line pulsing is stopped.
1 — An internal 1.5 k pull-up resistor is present on the DP line. The data line pulsing is started.
Remark: When port 1 is in peripheral mode or it plays the role of a peripheral while the OTG
functionality is enabled, it depends on the setting of DP_PULLUP and the V
connect the DP line to HIGH through a pull-up resister. V
present on the V
BUS
BUS
to 5 V using the charge pump
BUS
to V
to ground through a resistor
BUS
CC(I/O)
pin, V
Rev. 01 — 18 November 2009
through a resistor
BUS
= logic 1.
BUS
is an internal signal. When 5 V is
…continued
Hi-Speed USB OTG controller
BUS
SAF1761
© NXP B.V. 2009. All rights reserved.
sensing signal to
93 of 166