ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 95

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.10.2
17.10.3
17.10.4
17.10.5
8042B–AVR–06/10
TCNTnL – Timer/Counter n Register Low Byte
TCNTnH – Timer/Counter n Register High Byte
OCRnA – Timer/Counter n Output Compare Register A
OCRnB – Timer/Counter n Output Compare Register B
The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the Com-
pare Match on the following timer clock. Modifying the counter (TCNTnL) while the counter is
running, introduces a risk of missing a Compare Match between TCNTnL and the OCRnx Regis-
ters. In 16-bit mode the TCNTnL register contains the lower part of the 16-bit Timer/Counter n
Register.
When 16-bit mode is selected (the TCWn bit is set to one) the Timer/Counter Register TCNTnH
combined to the Timer/Counter Register TCNTnL gives direct access, both for read and write
operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers. See
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNTnL). A match can be used to generate an Output Compare interrupt.
In 16-bit mode the OCRnA register contains the low byte of the 16-bit Output Compare Register.
To ensure that both the high and the low bytes are written simultaneously when the CPU writes
to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
This temporary register is shared by all the other 16-bit registers. See
16-bit Mode” on page
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A match can be used to
generate an Output Compare interrupt.
Bit
0x26 (0x46)
Read/Write
Initial Value
Bit
0x27 (0x47)
Read/Write
Initial Value
Bit
0x28 (0x48)
Read/Write
Initial Value
Bit
0x29 (0x49)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
90.
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
”Accessing Registers in 16-bit Mode” on page
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
0
0
4
4
0
4
0
4
TCNTnL[7:0]
TCNTnH[7:0]
OCRnB[7:0]
OCRnA[7:0]
ATmega16HVB/32HVB
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
”Accessing Registers in
1
0
1
0
1
0
1
0
90.
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TCNTnH
TCNTnL
OCRnB
OCRnA
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