ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 216
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ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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30.7
30.7.1
30.7.2
8042B–AVR–06/10
Parallel Programming
Considerations for Efficient Programming
Signal Names
This section describes parameters, pin mapping, and commands used to parallel program and
verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the
ATmega16HVB/32HVB. Pulses are assumed to be at least 250 ns unless otherwise noted.
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
Address high byte needs only be loaded before programming or reading a new 256 word window
in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.
In this section, some pins of the ATmega16HVB/32HVB are referenced by signal names
describing their functionality during parallel programming, see
Table 30-13 on page
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in
When pulsing WR or OE, the command loaded determines the action executed. The different
Commands are shown in
programming characteristics.
Figure 30-3. Parallel Programming
EESAVE Fuse is programmed) and Flash after a Chip Erase.
PAGEL
XTAL1
BS2
BS1
WR
OE
X1
X0
+11.5 - 12.5V
217. Pins not described in the following table are referenced by pin names.
Table 30-16 on page
Table 30-15 on page
RESET
GND
218.
217.
Table 32-18 on page 241
ATmega16HVB/32HVB
V
FET
+4.0 - 25.0V
Figure 30-3 on page 216
RDY/BSY
DATA[7:0]
shows the Parallel
and
216
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