ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 83

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.2
17.3
17.4
8042B–AVR–06/10
Timer/Counter Clock Sources
Counter Unit
Definitions
pare Register. OCRnA contains the low byte of the word and OCRnB contains the higher byte of
the word. When accessing 16-bit registers, special procedures described in section
Registers in 16-bit Mode” on page 90
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The
output from the Clock Select logic is referred to as the timer clock (clk
Many register and bit references in this section are written in general form. A lower case “n”
replaces the module number, e.g. Timer/Counter number. A lower case “x” replaces the unit,
e.g. OCRnx and ICPnx describes OCRnA/B and ICP1/0x . However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 17-1.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source.
The Clock Select logic is controlled by the Clock Select (CSn2:0) bits located in the Timer/Coun-
ter Control Register n B (TCCRnB), and controls which clock source and edge the
Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
details on clock sources and prescaler, see
page 79
The main part of the 8-bit Timer/Counter is the counter unit.
block diagram of the counter and its surroundings.
Figure 17-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes 0.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or
0xFFFF (decimal 65535) in 16-bit mode.
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or
the value stored in the OCRnA Register.
Definitions
Table 17-1
DATA BUS
TCNTn
are also used extensively throughout the document.
must be followed.
count
”Timer/Counter0 and Timer/Counter1 Prescalers” on
Control Logic
top
ATmega16HVB/32HVB
TOVn
(Int.Req.)
clk
Tn
Figure 17-2 on page 83
Clock Select
( From Prescaler )
Detector
Edge
Tn
).
Tn
”Accessing
shows a
Tn
). For
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