ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 75

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-4.
15.3.2
8042B–AVR–06/10
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Alternate Functions of Port B
Overriding Signals for Alternate Functions in PA3:PA0
PA3/T1/PCINT3
PCINT3 • PCIE0
PCINT3 INPUT
T1 INPUT
These pins can serve as external interrupt
Port A to the overriding signals shown in
The Port B pins with alternate functions are shown in
Table 15-5.
The alternate pin configuration is as follows:
• MISO/PCINT11 – Port B, Bit7
MISO, Master Data input: Slave Data output pin for SPI channel. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB7. When the SPI is
enabled as a Slave, the data direction of this pin is controlled by DDB7. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB7 bit. When not operat-
ing in SPI mode, this pin can serve as an external interrupt source.
PCINT11: Pin Change Interrupt 11. This pin can serve as external interrupt source.
0
0
0
0
0
0
1
-
-
Port Pin
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Alternate Functions
MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt 11)
MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt 10)
SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt 9)
SS/PCINT8 (SPI Bus Slave Select input or Pin Change Interrupt 8)
PCINT7 (Pin Change Interrupt 7)
PCINT6 (Pin Change Interrupt 6)
CKOUT/PCINT5 (Clock output or Pin Change Interrupt 5)
PCINT4/ICP00 (Pin Change Interrupt 4
Port B Pins Alternate Functions
PA2/T0/PCINT2
PCINT2 • PCIE0
PCINT2 INPUT
T0 INPUT
0
0
0
0
0
0
1
-
-
PA1/ADC1/SGND/PCINT1
Figure 15-5 on page
VADSC • VADMUX=ADC0
VADSC • VADMUX=ADC0
DIDR1| (PCINT1 • PCIE0)
ADC1 INPUT/ SGND
sourceTable 15-4
PCINT1 INPUT
or Timer/Counter0 Input Capture Trigger
DIDR1
ATmega16HVB/32HVB
0
0
1
0
-
Table
15-5.
72.
relates the alternate functions of
PA0/ADC0/SGND/PCINT0
VADSC • VADMUX=ADC1
VADSC • VADMUX=ADC1
DIDR0 | (PCINT0 • PCIE0)
ADC0 INPUT/ SGND
PCINT0 INPUT
DIDR0
0
0
1
0
-
)
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