ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 141

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.2
8042B–AVR–06/10
BPCR – Battery Protection Control Register
locked, these registers cannot be accessed until the next hardware reset. This provides a safe
method for protecting the registers from unintentional modification by software runaway. It is rec-
ommended that software sets these registers shortly after reset, and then protect the registers
from further updates.
To lock these registers, the following algorithm must be followed:
1. In the same operation, write a logic one to BPPLE and BPPL.
2. Within the next four clock cycles, in the same operation, write a logic zero to BPPLE and
• Bits 7:6 – Reserved
These bits are reserved and will always read as zero.
• Bit 5 – EPID: External Protection Input Disable
When this bit is set, the External Protection Input is disabled and any External Protection Input
will be ignored. Note that this bit overrides the GPIO functionality in the External Protection Input
port. If not using the External Protection Input feature, it is recommended that this bit is always
set.
• Bit 4 – SCD: Short Circuit Protection Disabled
When the SCD bit is set, the Short-circuit Protection is disabled. The Short-circuit Detection will
be disabled, and any Short-circuit condition will be ignored.
• Bit 3 – DOCD: Discharge Over-current Protection Disabled
When the DOCD bit is set, the Discharge Over-current Protection is disabled. The Discharge
Over-current Detection will be disabled, and any Discharge Over-current condition will be
ignored.
• Bit 2 – COCD: Charge Over-current Protection Disable
When the COCD bit is set, the Charge Over-current Protection is disabled. The Charge Over-
current Detection will be disabled, and any Charge Over-current condition will be ignored.
• Bit 1 – DHCD: Discharge High-current Protection Disabled
When the DHCD bit is set, the Discharge High-current Protection is disabled. The Discharge
High-current Detection will be disabled, and any Discharge High-current condition will be
ignored.
• Bit 0 – CHCD: Charge High-current Protection Disable
When the CHCD bit is set, the Charge High-current Protection is disabled. The Charge High-cur-
rent Detection will be disabled, and any Charge High-current condition will be ignored.
Note:
Bit
(0xFD)
Read/Write
Initial Value
a logic one to BPPL.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCR register is written. Any writ-
ing to the BPCR register during this period will be ignored.
R
7
–
0
R
6
–
0
EPID
R/W
5
0
SCD
R/W
4
0
DOCD
ATmega16HVB/32HVB
R/W
3
0
COCD
R/W
2
0
DHCD
R/W
1
0
CHCD
R/W
0
0
BPCR
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