ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 153

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.4
25.4.1
8042B–AVR–06/10
Register Description
FCSR – FET Control and Status Register
• Bits 7:4 – Reserved
These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero.
• Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled
When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt-
age Recovery DUVR mode. See
charge FET” on page 150
during current protection or during internal reset, the DUVRD bit is overridden to one by hard-
ware in these cases. When this bit is set (one), Deep Under-voltage Recovery mode of the FET
Driver will be disabled. DUVR mode should not be used in 2-cell applications.
• Bit 2 – CPS: Current Protection Status
The CPS bit shows the status of the Current Protection. This bit is set (one) when a Current Pro-
tection is active, and cleared (zero) otherwise.
• Bit 1 – DFE: Discharge FET Enable
When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Discharge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared, Short-circuit, Discharge High-current and Discharge Over-current are disabled
regardless of the settings in the BPCR Register.
• Bit 0 – CFE: Charge FET Enable
When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Charge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared and the DUVRD bit is set, Charge High-current Protection and Charge Over-
current Protection are disabled regardless of the settings in the BPCR Register. When the
DUVRD bit is cleared, the charge FET will be enabled by DUVR mode regardless of the CFE
status.
Notes:
Bit
(0xF0)
Read/Write
Initial Value
1. Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
2. The NFET drivers require a minimum total cell voltage of 6V or higher or a charger connected
cycles + 3 CPU clock cycles is required between each time the FCSR register is written. Any
writing to the FCSR register during this period will be ignored.
to turn-on the FETs. Note that this limit only applies if the FET is disabled in advanced. If the
FET is already enabled, the FET will be fully operational in the entire voltage range of the
device (4-25V).
R
7
–
0
R
6
–
0
for details. To avoid that the FET driver tries to switch on the C-FET
R
”DUVR – Deep Under Voltage Recovery Mode without Pre-
5
–
0
R
4
–
0
DUVRD
ATmega16HVB/32HVB
R/W
3
1
CPS
R
2
0
DFE
R/W
1
0
CFE
R/W
0
0
FCSR
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