ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 122
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.4.4
8042B–AVR–06/10
DIDR0 – Digital Input Disable Register 0
• Bits 7:2 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
• Bit 1:0 – PA1DID:PA0DID: Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Port A pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the PA1:0 pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
Bit
(0x7E)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
T(K)
R
5
–
0
=
VADCH/L VPTAT CAL
-------------------------------------------------------------- -
R
4
–
0
16384
⋅
ATmega16HVB/32HVB
R
3
–
0
R
2
–
0
PA1DID
R/W
1
0
PA0DID
R/W
0
0
DIDR0
122
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