ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 188

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8042B–AVR–06/10
• Bit 6 – TWBCIE: TWI Bus Connect/Disconnect Interrupt Enable
When the TWBCIE bit and the I-bit in the Status Register are set, the TWI Bus Connect/Discon-
ne ct In terr upt is e nab le d. Th e corre spon ding inte rrup t is execu ted if a TWI Bus
Connect/Disconnect occurs, i.e., when the TWBCIE bit is set.
• Bit 5:3 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
• Bit 2:1 – TWBDT1, TWBDT0: TWI Bus Disconnect Time-out Period
The TWBDT bits decides how long both the TWI data (SDA) and clock (SCL) signals must be
low before generating the TWI Bus Disconnect Interrupt. The different configuration values and
their corresponding time-out periods are shown in
Table 27-8.
• Bit 0 – TWBCIP: TWI Bus Connect/Disconnect Interrupt Polarity
The TWBCIP bit decide if the TWI Bus Connect/Disconnect Interrupt Flag (TWBCIF) should be
set on a Bus Connect or a Bus Disconnect. If TWBCIP is cleared, the TWBCIF flag is set on a
Bus Connect. If TWBCIP is set, the TWBCIF flag is set on a Bus Disconnect.
TWBDT1
0
0
1
1
TW Bus Disconnect Time-out Period
TWBDT0
0
1
0
1
TWI Bus Disconnect Time-out Period
250 ms
500 ms
1000 ms
2000 ms
Table
ATmega16HVB/32HVB
27-8.
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