ATAVRSB202 Atmel, ATAVRSB202 Datasheet
ATAVRSB202
Specifications of ATAVRSB202
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ATAVRSB202 Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at ...
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Pin Configurations 1.1 TSSOP Figure 1-1. PA0(ADC0/SGND/PCINT0) PA1(ADC1/SGND/PCINT1) 1.2 Pin Descriptions 1.2.1 VFET High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in ”Voltage Regulator” on page 1.2.2 VCLMP10 Internal 10V clamping ...
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VREG Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regu- lator operation. For details, see 1.2.5 VREF Internal Voltage Reference for external decoupling. For details, see Temperature Sensor” on page 1.2.6 VREFGND Ground for ...
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PPI/NNI Unfiltered positive/negative input from external current sense resistor, used by the battery pro- tection circuit, for over-current and short-circuit detection. For details, see page 135. 1.2.15 NV/PV1/PV2/PV3/PV4 NV, PV1, PV2, PV3, and PV4 are the inputs for battery ...
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Overview The ATmega16HVB/32HVB is a monitoring and protection circuit for 3 and 4-cell Li-ion applica- tions with focus on highest safety including safe authentication, low cost and high utilization of the cell energy. The device contains secure authentication features ...
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... CISC microcontrollers. The device is manufactured using Atmel’s high voltage high density non-volatile memory tech- nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, through an SPI serial interface conventional non-volatile memory programmer On- chip Boot program running on the AVR core ...
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Comparison Between ATmega16HVB and ATmega32HVB The ATmega16HVB and ATmega32HVB differ only in memory size for Flash, EEPROM and internal SRAM. Table 2-1. 8042B–AVR–06/10 Table 2-1 summarizes the different configuration for the two devices. Configuration summary Device Flash ATmega16HVB 16K ...
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... All parameters contained in this datasheet are preliminary and based on characterization of ATmega16/32HVB. 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr Note: 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device ...
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AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...
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SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 7-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.5 Stack Pointer The Stack is mainly used for storing ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 7-4 vard architecture and the fast-access Register ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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AVR Memories 8.1 Overview This section describes the different memories in the ATmega16HVB/32HVB. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16HVB/32HVB features an EEPROM Memory for ...
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The ATmega16HVB/32HVB is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only ...
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Figure 8-3. 8.4 EEPROM Data Memory The ATmega16HVB/32HVB contains 512/1K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space ...
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Bits 7:0 – EEDR[7:0]: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains ...
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EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other- wise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 8.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 8.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write ...
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System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Voltage ADC Clock – clk The Voltage ADC is provided with a dedicated clock domain. The VADC clock is automatically prescaled relative to the System Clock Prescalers setting by the VADC Prescaler, giving a fixed VADC clock at 1 ...
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-2 on page Table 9-2. SUT2:0 111 Notes: 9.2.2 Slow RC Oscillator The Slow RC Oscillator provides a 131 kHz clock (typical value, ...
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To determine the accurate clock period as a function of die temperature, if needed by the application, the Oscillator Sampling Interface should be used. Refer to section Oscillator Sampling Interface” on page determine a fixed value ...
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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, and may be faster than the ...
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Figure 9-2. The osi_posedge signal pulses on each rising edge of the prescaled clock. This signal is not directly accessible by the CPU, but can be used to trigger the input capture function of Timer/Counter0. Using OSI in combination with ...
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Usage The Slow RC oscillator represents a highly predictable and accurate clock source over the entire temperature range and provides an excellent reference for calibrating the Fast RC oscillator run- time. Typically, runtime calibration is needed to provide an ...
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Register Description 9.8.1 FOSCCAL – Fast RC Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – FCAL[7:0]: Fast RC Oscillator Calibration Value The Fast RC Oscillator Calibration Register is used to trim the Fast RC Oscillator ...
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Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written ...
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Bit 4 – OSISEL0: Oscillator Sampling Interface Select 0 Table 9-6. • Bit 1 – OSIST: Oscillator Sampling Interface Status This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Figure 10-1. Sleep Mode State Diagram Sleep Interrupt ADC NRM Black-out Detection . Table 10-2. Active modules in different Sleep Modes Module RCOSC_FAST RCOSC_ULP RCOSC_SLOW OSI CPU Flash 8-bit Timer/16-bit Timer TWI/SMBus SPI V-ADC CC-ADC 8042B–AVR–06/10 Reset From all States ...
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Table 10-2. Active modules in different Sleep Modes (Continued) Module External Interrupts Battery Protection Watchdog Timer Voltage Regulator Bandgap Reference FET Driver (4) CHARGER_DETECT Notes: 1. Runs only when CC-ADC is enabled, or OSI is enabled and RCOSC_SLOW is selected ...
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If the current through the sense resistor is so small that the Coulomb Counter cannot measure it accurately, Regular Current detection should be enabled to reduce power consumption. The WDT keeps accurately track of the time so that battery self ...
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Refer to the section which pins are enabled. If the input buffer is enabled and the input signal is left floating or have ...
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Bits 7:4 – Reserved These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero. • Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0 These bits select between the four available sleep modes ...
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Bit 2 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 1 – PRTIM0: Power Reduction Timer/Counter0 ...
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System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 11-1. Reset Logic RESET 11.2.1 Power-on Reset and Charger Connect The Voltage Regulator will not start up until the Charger Detect module has enabled it. Before this happens the chip will be in Power-off mode and only the Charger ...
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Figure 11-2. Powering up ATmega16HVB/32HVB 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. ...
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Figure 11-4. Watchdog Reset During Operation 11.2.4 Brown-out Detection ATmega16HVB/32HVB has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level V CC hysteresis to ensure spike free Brown-out ...
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Watchdog Timer 11.4.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • Possible Hardware fuse Watchdog always ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Register Description 11.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:5 – Reserved These bits are reserved in the ...
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Bit 6 – WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog ...
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Table 11-2. WDP3 Note: 8042B–AVR–06/10 Watchdog Timer Prescale Select WDP2 WDP1 WDP0 ...
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Interrupts 12.1 Overview ...
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Table 12-1. Vector No Notes: If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. Table 12-2 BOOTRST and IVSEL settings. If the ...
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TIM1_COMPB 0x001E jmp TIM1_OVF 0X0020 jmp TIM0_IC 0x0022 jmp TIM0_COMPA 0x0024 jmp TIM0_COMPB 0x0026 jmp TIM0_OVF 0x0028 jmp TWI_BUS_CD 0x002A jmp TWI 0x002C jmp SPI, STC 0x002E jmp VADC 0x0030 jmp CCADC_CONV 0x0032 jmp CCADC_REC_CUR 0x0034 jmp CCADC_ACC ...
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SPM_RDY ; .org 0x4C00 0x4C00 RESET: ldi 0x4C01 out 0x4C02 ldi 0x4C03 out 0x4C04 sei 0x4C05 <instr> When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in ...
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Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void 12.4 Register Description 12.4.1 MCUCR – MCU Control ...
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IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written ...
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External Interrupts 13.1 Overview The External Interrupts are triggered by the INT3:0 pin or any of the PCINT11:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT11:0 pins are configured as outputs. This ...
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Table 13-1. ISCn1 Note: 13.2.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved ins the ATmega16HVB/32HVB, and will always read as zero. • ...
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PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bits 7:2 – Reserved These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero. • Bit 1 – PCIE1: Pin Change Interrupt Enable ...
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Bit 7:0 – PCINT[11:4]: Pin Change Enable Mask 15:8 These bits select whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[11:4] is set and the PCIE1 bit in EIMSK is set, pin change interrupt is ...
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High Voltage I/O Ports 14.1 Overview All high voltage AVR ports have true Read-Modify-Write functionality when used as general dig- ital I/O ports. This means that the state of one port pin can be changed without unintentionally changing the ...
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High Voltage Ports as General Digital I/O The high voltage ports are high voltage tolerant open collector output ports. In addition they can be used as general digital inputs. pin, here generically called Pxn. Figure 14-2. General High Voltage ...
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Overview 14.4 Alternate Port Functions The High Voltage I/O has alternate port functions in addition to being general digital I/O. 14-3 shows how the port pin control signals from the simplified overridden by alternate functions. Figure 14-3. High Voltage ...
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Table 14-1. Signal Name PVOE PVOV DIEOE DIEOV DI 14.4.1 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-2. Port Pin The alternate pin configuration is as follows: • INT0/ EXTPROT – ...
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INT3/ SDA – Port C, Bit3 INT3: External Interrupt Source 3. This pin can serve as external interrupt source. INT3 can be used as an interrupt pin regardless of whether another function is enabled or not. SDA: SM Bus ...
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Low Voltage I/O-Ports 15.1 Overview All low voltage AVR ports have true Read-Modify-Write functionality when used as general digi- tal I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 15.2 Low Voltage Ports as General Digital I/O The low voltage ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 15-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly Code Example C Code Example unsigned char i; Note: 15.2.5 Digital Input Enable and Sleep Modes As shown in input of the schmiSchmidtt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-save ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Note: Table 15-2 ure 15-5 on page 72 generated internally in the modules having the alternate function. Table 15-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions ...
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Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 15-3. The alternate pin configuration is as follows: • ADC0/SGND/PCINT0 – Port A, Bit0 ADC0: Voltage ADC Channel0. This pin can serve as ...
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These pins can serve as external interrupt Port A to the overriding signals shown in Table 15-4. Overriding Signals for Alternate Functions in PA3:PA0 Signal Name PA3/T1/PCINT3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE ...
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MOSI/PCINT10 – Port B, Bit6 MOSI, SPI Master Data output: Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB6. When the ...
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Table 15-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 15-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8042B–AVR–06/10 Overriding Signals for Alternate Functions in PB7:PB4 PB7/MISO/PCINT11 PB6/MOSI/PCINT10 ...
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Register Description 15.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
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Timer/Counter0 and Timer/Counter1 Prescalers 16.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1.1 Internal Clock Source The Timer/Counter can be ...
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External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro- nized (sampled) signal is ...
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Register Description 16.3.1 TCCRnB – Timer/Counter n Control Register B Bit (0x80)(0x81) Read/Write Initial Value • Bits – CSn2, CSn1, CSn0: Clock Select0, Bit 2, 1, and 0 The Clock Select n bits 2, 1, and ...
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Timer/Counter (T/C0,T/C1) 17.1 Features • Clear Timer on Compare Match (Auto Reload) • Input Capture unit • Four Independent Interrupt Sources (TOVn, OCFnA, OCFnB, ICFn) • 8-bit Mode with Two Independent Output Compare Units • 16-bit Mode with One ...
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Register. OCRnA contains the low byte of the word and OCRnB contains the higher byte of the word. When accessing 16-bit registers, special procedures described in section Registers in 16-bit Mode” on page 90 The Timer/Counter can be clocked ...
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Signal description (internal signals): count clk top The counter is incremented at each timer clock (clk restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits located in the Timer/Counter Control Register (TCCRnA). For more ...
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OCRnA. The OCRnA defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting ...
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TCNTn, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before Compare Match can occur. As for the 16-bit Mode, the TOVn ...
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Input Capture mode the Output Compare Unit cannot be used as there are no free Output Compare Register(s). Even though the Input Capture register is called ICRn in this sec- tion referring to the Output ...
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I/O bit location). For measuring frequency only, the trigger edge change is not required. Table 17-3. ICS0 0 1 Note: Table 17-4. ICS1 0 1 Note: 17.7 Output Compare Unit The ...
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Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnA ...
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Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 17-9 on page 90 Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f 17.9 Accessing Registers in 16-bit Mode In 16-bit mode (the TCWn bit is set ...
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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B registers. Assembly Code Example C Code Example Note: The ...
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The following code examples show how atomic read of the TCNTn register contents. Reading any of the OCRn register can be done by using the same principle. Assembly Code Example TIMn_ReadTCNTn: C Code Example unsigned int TIMn_ReadTCNTn( ...
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The following code examples show how atomic write of the TCNTnH/L register con- tents. Writing any of the OCRnA/B registers can be done by using the same principle. Assembly Code Example TIMn_WriteTCNTn: C Code Example void TIMn_WriteTCNTn( ...
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Register Description 17.10.1 TCCRnA – Timer/Counter n Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – TCWn: Timer/Counter Width When this bit is written to one 16-bit mode is selected. Timer/Counter n width is set ...
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TCNTnL – Timer/Counter n Register Low Byte Bit 0x26 (0x46) Read/Write Initial Value The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) ...
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In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis- ter. To ensure that both the high and the low bytes are written simultaneously when the CPU writes to these registers, the access is ...
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Bit 2 – OCFnB: Output Compare Flag n B The OCFnB bit is set when a Compare Match occurs between the Timer/Counter and the data in OCRnB – Output Compare Register n B. OCFnB is cleared by hardware when ...
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SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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Table 18-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8042B–AVR–06/10 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock rate ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8042B–AVR–06/10 (1) SPI_SlaveInit: ; Set ...
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SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 8042B–AVR–06/10 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 ...
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Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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The SPI interface on the ATmega16HVB/32HVB is also used for program memory and EEPROM downloading or uploading. See verification. 18.5.3 SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used ...
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Coulomb Counter – Dedicated Fuel Gauging Sigma-delta ADC 19.1 Features • Sampled System Coulomb Counter • Low Power Sigma-Delta ADC Optimized for Coulomb Counting • Instantaneous Current Output with 3.9 ms Conversion Time – 13 bit Resolution (including sign ...
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In normal conversion mode two different output values are provided, Instantaneous Current and Accumulate Current. The Instantaneous Current Output has a short conversion time at the cost of lower resolution. The Accumulate Current Output provides a highly accurate current measure- ...
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Figure 19-3. Accumulation Current Conversions Enable Accumulation Interrupt Accumulation Data Read byte 1 Read byte 2 Read byte 3 Read byte 4 19.4 Regular Current Detection Operation By setting the CADSE bit in CADCSRA the CC-ADC will enter a special ...
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Configuration and Usage While the CC-ADC is converting, the CPU can enter sleep mode and wait for an interrupt. After adding the conversion data for the Coulomb Counting, the CPU can go back to sleep again. This reduces the ...
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Bits 4:3 – CADAS1:0: CC-ADC Accumulate Current Select The CADAS bits select the conversion time for the Accumulate Current output as shown in the Table 19-1. Table 19-1. Note: • Bits 2:1 – CADSI1:0: CC-ADC Current Sampling Interval The ...
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Bit 5 – CADRCIE: CC-ADC Regular Current Interrupt Enable When the CADRCIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Regular Current Interrupt is enabled. • Bit 4 – CADICIE: CC-ADC ...
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Table 19-3. CADVSE 19.7.4 CADICH and CADICL – CC-ADC Instantaneous Current Bit (0xE5) (0xE4) Bit Read/Write Initial Value When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two registers. CADIC15:0 represents the converted result in ...
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CADRCC – CC-ADC Regular Charge Current Bit (0xE9) Read/Write Initial Value The CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with ...
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Table 19-5. Voltage (µV) Current (mA) Note: The CC-ADC Regular Discharge Current Register does not affect the setting of the CC-ADC Conversion Complete Interrupt Flag. 8042B–AVR–06/10 Programmable Range for the Regular Discharge Current Level mΩ SENSE R ...
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Voltage ADC – 7-channel General Purpose 12-bit Sigma-Delta ADC 20.1 Features • 12-bit Resolution • 519µs Conversion Time @ 1 MHz clk • Four Differential Input Channels for Cell Voltage Measurements • Three Single Ended Input Channels • 0.2x ...
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Power-off mode. Note that the bandgap voltage reference must be enabled and disabled sepa- rately, see Figure 20-2. Voltage ADC Conversion Diagram Start Conversion Interrupt Conversion Result To perform a V-ADC conversion, the analog input channel must first be selected ...
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Cell inputs The V-ADC features one input channel for each battery cell to be able to measure each cell indi- vidually and to measure the total battery voltage through the input pins NV, PV1, PV2, PV3 and PV4. Note ...
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Register Description 20.4.1 VADMUX – V-ADC Multiplexer Selection Register Bit (0x7C) Read/Write Initial Value • Bit 7:4 – Reserved These bits are reserved in the ATmega16HVB/32HVB and will always read as zero. • Bit 3:0 – VADMUX[3:0]: V-ADC Channel ...
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VADSC will read as one as long as the conversion is not finished. When the conversion is com- plete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be cleared when the VADEN bit ...
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DIDR0 – Digital Input Disable Register 0 Bit (0x7E) Read/Write Initial Value • Bits 7:2 – Reserved These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when DIDR0 ...
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Voltage Reference and Temperature Sensor 21.1 Features • Accurate Voltage Reference of 1.100V • Voltage Reference Calibration Interface • Internal Temperature Sensor • External Decoupling for Optimum Noise Performance • Short Circuit Detection on the External Decoupling pin • ...
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Operation When the device is in power-off state, the Voltage Reference will be switched off. After a Power- on reset condition the Voltage Reference will automatically be enabled. By default the Bandgap Buffer will be enabled as the buffered ...
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NFET driver (OC/OD or enter DUVR operation), Battery Protection, V-ADC or CC-ADC. Settling time is needed when the Buffer is enabled by software, or after a reset condition where the buffer is automatically enabled. 8042B–AVR–06/10 ATmega16HVB/32HVB ...
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... Minimum VREF: 000000, maximum VREF: 111111. Step size is approxi- mately 2 mV. The application software should read the Atmel factory calibration value and store it to the BGCCR register. See ”Reading the Signature Row from Software” on page 199 for details ...
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Figure 21-2. 21.6.3 BGCSR – Bandgap control and Status Register Bit (0xD2) Read/Write Initial Value • Bits 7:6 – Reserved These bits are reserved and will always read as zero. • Bit 5 – BGD: Bandgap Disable Setting this bit ...
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Bit 0 – BGSCDIE: Bandgap Short Circuit Detection Interrupt Enable When this bit is set, the Bandgap Short Circuit Detection Interrupt is enabled. The corresponding interrupt is executed if a short-circuit is detected on the External Decoupling Pin for ...
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Charger Detect 22.1 Features • Operates directly from VFET supply • Detects when a charger is connected or disconnected by monitoring the BATT pin • Controls the operation state of the device by automatically enable/disable the internal Voltage Regulator ...
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Operation The Charger Detect module is supplied directly from the VFET pin. When operating, the Charger Detect will monitor the voltage of the BATT pin and detect whether a charger is present or not. When the voltage on the ...
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When disabling the Charge-FET the Charger Detect module is automatically enabled and a charger appear to be connected. 22.4 Register Description 22.4.1 CHGDCSR – Charger Detect Control and Status Register Bit (0xD4) Read/Write Initial Value • Bit 7:5 – ...
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Voltage Regulator 23.1 Features • Input voltage from 4-25V • Fixed output voltage of 3.3V • Battery Pack Short Detection • Black-out Detection (BLOD) 23.2 Overview ATmega16HVB/32HVB get its voltage supply through the VFET terminal. Operating range at the ...
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Regulator Start-up When the chip is in power-off mode the Voltage Regulator will be off and there will be no con- nection between VFET and VREG. The regulator is started when the Charger Detect module detects that a charger ...
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Register Description 23.6.1 ROCR – Regulator Operating Condition Register Bit (0xC8) Read/Write Initial Value • Bit 7 – ROCS: ROC Status This bit is set when the Voltage Regulator operates in the Battery Pack Short mode, and cleared otherwise. ...
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Battery Protection 24.1 Features • Short-circuit Protection • Discharge Over-current Protection • Charge Over-current Protection • Discharge High-current Protection • Charge High-current Protection • External Protection Input • Programmable and Lockable Detection Levels and Reaction Times • Autonomous Operation ...
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Operation The Current Battery Protections (CBP) monitors the cell current by sampling the shunt resistor voltage at the PPI/NNI input pins. A differential operational amplifier amplifies the voltage with a suitable gain. The output from the operational amplifier is ...
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When the Discharge High-current Protection is activated, the external D-FET and C-FET are dis- abled and a Current Protection Timer is started. This timer ensures that the FETs are disabled for at least one second. The application software must then ...
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The user must disable the External Protection Input in the BPCR register before the port can be used as a normal port. Also during the reset sequence, the External Protection Input may disable the FETs. Conse- quently, if the External ...
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Optimizing Usage for Low Power Consumption In order to reduce power consumption, Short-circuit, Discharge High-current and Discharge Over-current Protection are automatically deactivated when the D-FET is disabled. The Charge Over-current and Charge High-current Protection are disabled when the C-FET ...
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Battery Protection CPU Interface The Battery Protection CPU Interface is illustrated in Figure 24-2. Battery Protection CPU Interface Battery Protection Parameter Lock Each protection originating from the Current Battery Protection module has an Interrupt Flag. Each Flag can be ...
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This provides a safe method for protecting the registers from unintentional modification by software runaway rec- ommended that software sets these registers shortly after reset, and then ...
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BPSCTR – Battery Protection Short-current Timing Register Bit (0xFA) Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the ATmega16HVB/32HVB and will always read as zero. • Bit 6:0 – SCPT[6:0]: Short-current Protection Timing These ...
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Table 24-3. Notes: Note: 24.7.5 BPHCTR – Battery Protection High-current Timing Register Bit (0xFC) Read/Write Initial Value • Bit 7:6 – Reserved These bits are reserved in the ATmega16HVB/32HVB and will always read as zero. • Bit 5:0 – HCPT[5:0]: ...
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Table 24-4. Notes: Note: 24.7.6 BPSCD – Battery Protection Short-circuit Detection Level Register Bit (0xF5) Read/Write Initial Value • Bits 7:0 – SCDL[7:0]: Short-circuit Detection Level These bits sets the R as defined in Note: 24.7.7 BPDOCD – Battery Protection ...
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BPCOCD – Battery Protection Charge-Over-current Detection Level Register Bit (0xF7) Read/Write Initial Value • Bits 7:0 –COCDL[7:0]: Charge Over-current Detection Level These bits sets the R Table 24-5 on page Note: 24.7.9 BPDHCD – Battery Protection Discharge-High-current Detection Level ...
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Table 24-5. All other values 24.7.11 BPIMSK – Battery Protection Interrupt Mask Register Bit (0xF2) Read/Write Initial Value • Bit 7:5 – Reserved These bits are reserved and will always read as zero. • Bit 4 – SCIE: Short-circuit Protection ...
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Bit 3 – DOCIE: Discharge Over-current Protection Activated Interrupt The DOCIE bit enables interrupt caused by the Discharge Over-current Protection Activated Interrupt. • Bit 2 – COCIE: Charge Over-current Protection Activated Interrupt The COCIE bit enables interrupt caused by ...
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FET Driver 25.1 Features • High side N-channel FET driver for controlling Charge and Discharge FETs in Li-ion battery application • Optional Deep Under-voltage Recovery mode allowing normal operation while charging Deeply discharged battery cells from 0-volt without an ...
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For safe operation the FET driver automatically turns off both the Charge and Discharge FET if the autonomous Battery Protection circuitry (see illegal current condition. If such conditions occur, software is not allowed to turn on the FETs until the ...
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The C-FET/D-FETs is switched on by pumping the gate OC/OD above the source voltage (PVT/BATT) of the external FET. When the gate-source voltage has reached a level higher than typically 13V the pumping frequency is reduced and is regulated to ...
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DUVR mode and enable the C-FET before the charger sees this limit. When the battery is started from a power-off condition by connecting a legal charger, SW should determine whether to allow charging or not ...
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The total cell voltage has reached 5V. DUVR mode is disabled and the C-FET can be fully enabled. DUVR mode should be disabled before the C-CFET is enabled. VFET and Pack+ will therefore rise to the charger voltage for ...
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Register Description 25.4.1 FCSR – FET Control and Status Register Bit (0xF0) Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero. • Bit 3 – DUVRD: Deep ...
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Cell Balancing 26.1 Overview ATmega16HVB/32HVB incorporates cell balancing FETs. The chip provides one cell balancing FET for each battery cell in series. The FETs are directly controlled by the application software, allowing the cell balancing algorithms to be implemented ...
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Register Description 26.2.1 CBCR – Cell Balancing Control Register Bit (0xF1) Read/Write Initial Value • Bit 7:4 – Reserved These bits are reserved in the ATmega16HVB/32HVB and will always read as zero. • Bit 3 – CBE4: Cell Balancing ...
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Serial Interface 27.1 Features • Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space allows up ...
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TWI Terminology The following definitions are frequently encountered in this section. Table 27-1. Term Master Slave Transmitter Receiver 27.2.2 Electrical Interconnection As depicted in pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements ...
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START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a ...
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Figure 27-4. Address Packet Format 27.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and ...
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Figure 27-6. Typical Data Transmission SDA SCL 27.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if ...
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Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration. Note that a ...
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Overview of the TWI Module The TWI module is comprised of several submodules, as shown in isters are accessible through the AVR data bus. Figure 27-9. Overview of the TWI Module 27.5.1 SCL and SDA Pins These pins interface ...
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Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is con- trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI ...
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Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag ...
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Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free ...
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TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to ...
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Assembly code example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, r16 wait1: in r16,TWCR 2 sbrs r16,TWINT rjmp wait1 in r16,TWSR andi r16, 0xF8 3 cpi r16, START brne ERROR r16, SLA_W ldi out TWDR, r16 ldi r16, (1<<TWINT) ...
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Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. ...
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Figure 27-11. Data Transfer in Master Transmitter Mode SDA SCL A START condition is sent by writing the following value to TWCR: TWCR Value TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one ...
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A REPEATED START condition is generated by writing the following value to TWCR: TWCR Value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again new slave without transmitting a STOP ...
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Figure 27-12. Formats and States in the Master Transmitter Mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost ...
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Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a slave transmitter (see Figure mat of the following address packet determines whether Master Transmitter or Master Receiver mode entered. ...
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TWCR Value A REPEATED START condition is generated by writing the following value to TWCR: TWCR Value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again new slave without transmitting ...
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Figure 27-14. Formats and States in the Master Receiver Mode Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration ...
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TWAR Value The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ...
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Table 27-4. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface Are 0 Hardware 0x60 Own SLA+W has been received; ACK has been returned 0x68 Arbitration lost in ...
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Figure 27-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure zero or are masked to zero. Figure 27-17. Data Transfer in Slave Transmitter Mode SDA SCL To initiate ...
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While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may ...
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Figure 27-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (TWEA ...
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Table 27-6. Miscellaneous States Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an illegal START ...
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Figure 27-20. An Arbitration Example SDA SCL Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the ...
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Bus Connect/Disconnect for Two-wire Serial Interface The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura- tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected. Figure 27-22 ...
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Register Description 27.10.1 TWBR – TWI Bit Rate Register Bit (0xB8) Read/Write Initial Value • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency ...
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However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the Bus Master status. TWSTA is cleared ...
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Table 27-7. To calculate bit rates, see in the equation. 27.10.4 TWDR – TWI Data Register Bit (0xBB) Read/Write Initial Value In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last ...
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Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. 27.10.6 TWAMR – TWI (Slave) Address Mask Register Bit (0xBD) Read/Write Initial ...
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Bit 6 – TWBCIE: TWI Bus Connect/Disconnect Interrupt Enable When the TWBCIE bit and the I-bit in the Status Register are set, the TWI Bus Connect/Discon terr upt is e nab corre ...
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On-chip Debug System 28.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. ...
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Boot Loader Support – Read-While-Write Self-Programming 29.1 Features • Read-While-Write Self-Programming • Flexible Boot Memory Size • High Security (Separate Boot Lock Bits for a Flexible Protection) • Separate Fuse to Select Reset Vector • Optimized Page • Code ...
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Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft- ware update is dependent on which address that is being programmed. In addition to the two sections ...
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Figure 29-1. Read-While-Write vs. No Read-While-Write 8042B–AVR–06/10 Read-While-Write (RWW) Section Z-pointer No Read-While-Write Addresses RWW (NRWW) Section Section Code Located in NRWW Section Can be Read During the Operation ATmega16HVB/32HVB Z-pointer Addresses NRWW Section CPU is Halted During the Operation ...
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Figure 29-2. Memory Sections Note: 29.5 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set ...
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Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via the TWI interface. Alternatively, the Boot ...
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Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit ZH (R31) ZL (R30) Since the Flash is organized in pages (see be treated as having two different sections. One section, consisting of the ...
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Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buf- fer is filled ...
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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...
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Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the LBSET and SPMEN bits in ...
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Table 29-3. Signature Byte Description SLOW RC Temp Prediction L SLOW RC Temp Prediction H ULP RC FRQ SLOW RC FRQ ULP RC Temp Prediction Coefficient L ULP RC Temp Prediction Coefficient H ULP RC Period L ULP RC Period ...