ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 156

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27. 2-wire Serial Interface
27.1
27.2
8042B–AVR–06/10
Features
Two-wire Serial Interface Bus Definition
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The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
When the TWI is not used, power consumption can be minimized by writing the PRTWI bit in
PRR0 to one. See
the PRTWI bit.
Figure 27-1. TWI Bus Interconnection
Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Supports SM Bus transfer speeds from 10 to 100kHz
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when AVR is in Sleep Mode
SDA
SCL
Device 1
”PRR0 – Power Reduction Register 0” on page 40
Device 2
Device 3
........
ATmega16HVB/32HVB
Device n
V
BUS
R1
for details on how to use
R2
156