ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 94

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.10 Register Description
17.10.1
8042B–AVR–06/10
TCCRnA – Timer/Counter n Control Register A
• Bit 7 – TCWn: Timer/Counter Width
When this bit is written to one 16-bit mode is selected. Timer/Counter n width is set to 16-bits
and the Output Compare Registers OCRnA and OCRnB are combined to form one 16-bit Output
Compare Register. Because the 16-bit registers TCNTnH/L and OCRnB/A are accessed by the
AVR CPU via the 8-bit data bus, special procedures must be followed. These procedures are
described in section
• Bit 6 – ICENn: Input Capture Mode Enable
The Input Capture Mode is enabled when this bit is written to one.
• Bit 5 – ICNCn: Input Capture Noise Canceler
Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-
vated, the input from the Input Capture Source is filtered. The filter function requires four
successive equal valued samples of the Input Capture Source for changing its output. The Input
Capture is therefore delayed by four System Clock cycles when the noise canceler is enabled.
• Bit 4 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Source that is used to trigger a capture event.
When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the
ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is trig-
gered according to the ICESn setting, the counter value is copied into the Input Capture
Register. The event will also set the Input Capture Flag (ICFn), and this can be used to cause an
Input Capture Interrupt, if this interrupt is enabled.
• Bit 3 – ICSn: Input Capture Select
When written logic one, this bit enables the input capture function in Timer/Counter n to be trig-
gered by the alternative Input Capture Source. To make the comparator trigger the
Timer/Counter n Input Capture interrupt, the TICIEn bit in the Timer Interrupt Mask Register
(TIMSK) must be set. See
• Bits 2:1 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
• Bit 0 – WGMn0: Waveform Generation Mode
This bit controls the counting sequence of the counter, the source for maximum (TOP) counter
value, see
Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see
Timing Diagrams” on page
Bit
0x24 (0x44)
Read/Write
Initial Value
Figure 17-6 on page
TCWn
R/W
7
0
”Accessing Registers in 16-bit Mode” on page
ICENn
R/W
6
0
Table 17-3 on page 88
89).
89. Modes of operation supported by the Timer/Counter unit are:
ICNCn
R/W
5
0
ICESn
R/W
4
0
and
ATmega16HVB/32HVB
ICSn
R/W
3
0
Table 17-4 on page
R
2
–
0
90.
R
1
–
0
88.
WGMn0
R/W
”Timer/Counter
0
0
TCCRnA
94