ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 84

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5
Table 17-2.
17.5.1
17.5.2
8042B–AVR–06/10
Mode
0
1
2
3
4
5
Modes of Operation
Normal 8-bit Mode
Clear Timer on Compare Match (CTC) 8-bit Mode
ICENn
0
0
0
0
1
1
Modes of Operation
TCWn
0
0
1
1
0
1
Signal description (internal signals):
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits
located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk
priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is
set when the counter reaches the maximum value and it can be used for generating a CPU
interrupt.
The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable
(ICENn) and the Waveform Generation Mode (WGMn0)bits in
Control Register A” on page
In the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes its
maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00), see
page 84
the TCNTnL becomes zero. The TOVn Flag in this case behaves like a ninth bit, except that it is
only set, not cleared. However, combined with the timer overflow interrupt that automatically
clears the TOVn Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal 8-bit mode, a new counter value can be written anytime. The
Output Compare Unit can be used to generate interrupts at some given time.
In Clear Timer on Compare or CTC mode, the OCRnA Register is used to manipulate the coun-
ter resolution, see
WGMn0
count
clk
top
0
1
0
1
0
0
for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock cycle as
Tn
Timer/Counter Mode
Normal 8-bit Mode
8-bit CTC
16-bit Mode
16-bit CTC
8-bit Input Capture
mode
16-bit Input Capture
mode
”Timer/Counter Timing Diagrams” on page
Table 17-2 on page 84
of Operation
94.
Increment or decrement TCNTn by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNTn has reached maximum value.
Table 17-2 on page 84
for bit settings. In CTC mode the counter is cleared to
OCRnB,
0xFFFF
0xFFFF
OCRnA
OCRnA
0xFF
0xFF
TOP
Tn
is present or not. A CPU write overrides (has
ATmega16HVB/32HVB
Tn
) until it passes its TOP value and then
shows the different Modes of Operation.
Update of
Immediate
Immediate
Immediate
Immediate
89. clk
OCRx at
–
–
”TCCRnA – Timer/Counter n
Tn
Tn
can be generated from an
in the following.
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFF)
MAX (0xFF)
MAX (0xFF)
TOV Flag
Set on
Table 17-2 on
84