ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 168

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.7
27.7.1
8042B–AVR–06/10
Transmission Modes
Master Transmitter Mode
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
In
TWINT flag is set. The numbers in the circles show the status code held in TWSR, with the pres-
caler bits masked to zero. At these points, actions must be taken by the application to continue
or complete the TWI transfer. The TWI transfer is suspended until the TWINT flag is cleared by
software.
When the TWINT flag is set, the status code in TWSR is used to determine the appropriate soft-
ware action. For each status code, the required software action and details of the following serial
transfer are given in
bits are masked to zero in these tables.
In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see
Figure 27-11 on page
mitted. The format of the following address packet determines whether Master Transmitter or
Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R
is transmitted, MR mode is entered. All the status codes mentioned in this section assume that
the prescaler bits are zero or are masked to zero.
Figure 27-12 on page 171
S:
Rs:
R:
W:
A:
A:
Data:
P:
SLA:
Table 27-2 on page 170
169). In order to enter a Master mode, a START condition must be trans-
to
START condition
REPEATED START condition
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)
8-bit data byte
STOP condition
Slave Address
Figure 27-18 on page
to
Table 27-5 on page
ATmega16HVB/32HVB
180, circles are used to indicate that the
179. Note that the prescaler
168