ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 111

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6
19.7
19.7.1
8042B–AVR–06/10
Configuration and Usage
Register Description
CADCSRA – CC-ADC Control and Status Register A
While the CC-ADC is converting, the CPU can enter sleep mode and wait for an interrupt. After
adding the conversion data for the Coulomb Counting, the CPU can go back to sleep again. This
reduces the CPU workload, and allows more time spent in low power modes, reducing power
consumption.
To use the CC-ADC the bandgap voltage reference must be enabled separately, see
Reference and Temperature Sensor” on page
The CC-ADC will not consume power when CADEN is cleared. It is therefore recommended to
switch off the CC-ADC whenever the Coulomb Counter or Regular Current Detection functions
are not used. The CC-ADC is automatically disabled in Power-off mode.
After the CC-ADC is enabled by setting the CADEN bit, the first four conversions do not contain
useful data and should be ignored. This also applies after clearing the CADSE bit, or after
changing the CADPOL or CADVSE bits.
The conversion times and sampling intervals are controlled by the Ultra Low Power RC Oscilla-
tor (see
To obtain accurate coulomb counting results, the actual conversion time should be calculated.
Refer to
• Bit 7 – CADEN: CC-ADC Enable
When the CADEN bit is cleared (zero), the CC-ADC is disabled, and any ongoing conversions
will be terminated. When the CADEN bit is set (one), the CC-ADC will continuously measure the
voltage drop over the external sense resistor R
disabled.
Note that the bandgap voltage reference must be enabled separately, see
and Temperature Sensor” on page
• Bit 6 – CADPOL: CC-ADC Polarity
The CADPOL bit is used to change input sampling polarity in the Sigma Delta Modulator. Writing
this bit to one, the polaritiy will be negative. When the bit is zero, the polarity will be positive.
• Bit 5 – CADUB: CC-ADC Update Busy
The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ-
ten to CADCSRA, CADCSRC, CADRCC or CADRDC, this value must be synchronized to the
CC-ADC clock domain. Subsequent writes to these registers will be blocked during this synchro-
nization. Synchronization of one of the registers will block updating of all the others. The CADUB
bit will be read as one while any of these registers is being synchronized, and will be read as
zero when neither register is being synchronized.
Bit
(0xE6)
Read/Write
Initial Value
”Ultra Low Power RC Oscillator” on page
”System Clock and Clock Options” on page 25
CADEN
R/W
7
0
CADPOL
R/W
6
0
CADUB
R
5
0
123.
CADAS1
R/W
4
0
123.
CADAS0
SENSE
27), and will depend on its actual frequency.
R/W
3
0
ATmega16HVB/32HVB
for details.
. In Power-off, the CC-ADC is always
CADSI1
R/W
2
0
CADSI0
R/W
1
0
”Voltage Reference
CADSE
R/W
0
0
CADCSRA
”Voltage
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