ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 106
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.5.2
8042B–AVR–06/10
SPSR – SPI Status Register
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 18-5.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5:1 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
osc
0
0
0
0
1
1
1
1
/4 or lower.
Relationship Between SCK and the Oscillator Frequency
SPIF
R
7
0
Table 18-5 on page
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
R
5
–
0
SPR0
106). This means that the minimum SCK period will
R
4
–
0
0
1
0
1
0
1
0
1
ATmega16HVB/32HVB
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
R
1
–
0
SPI2X
R/W
0
0
SPSR
osc
106
is
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