ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 49

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
11.5.1
11.5.2
8042B–AVR–06/10
Register Description
MCUSR – MCU Status Register
WDTCSR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bits 7:5 – Reserved
These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero.
• Bit 4 – OCDRF: OCD Reset Flag
This bit is set if a debugWIRE Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BODRF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. In the case of a Power-on Reset, both the BODRF
and the PORF will be set. The BODRF is reset by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the reset flags.
• Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
(0x60)
Read/Write
Initial Value
WDIF
R/W
7
0
R
7
–
0
WDIE
R/W
6
0
R
6
–
0
WDP3
R/W
5
0
R
5
–
0
WDCE
OCDRF
R/W
R/W
4
0
4
WDE
ATmega16HVB/32HVB
WDRF
R/W
R/W
X
3
3
See Bit Description
WDP2
BODRF
R/W
R/W
2
0
2
WDP1
EXTRF
R/W
R/W
1
0
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCSR
MCUSR
49