ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 58

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. External Interrupts
13.1
13.2
13.2.1
8042B–AVR–06/10
Overview
Register Description
EICRA – External Interrupt Control Register A
The External Interrupts are triggered by the INT3:0 pin or any of the PCINT11:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT11:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the
58. When the external interrupt is enabled and is configured as level triggered, the interrupt will
trigger as long as the pin is held low. Interrupts are detected asynchronously. This implies that
these interrupts can be used for waking the part also from sleep modes other than Idle mode.
The I/O clock is halted in all sleep modes except Idle mode.
The Pin change interrupt PCI1 will trigger if any enabled PCINT11:4 pin toggles and Pin change
interrupts PCI0 will trigger if any enabled PCINT3:0 pin toggles. PCMSK1 and PCMSK0 Regis-
ters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT11:0 are detected asynchronously. This implies that these interrupts can be used for wak-
ing the part also from sleep modes other than Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-save, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT fuses as described in
Systems and their Distribution” on page
• Bits 7:0 – ISCn: External Interrupt Sense Control Bits
The External Interrupts 3:0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in
11 on page 235
interrupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an
interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt
Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt
flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis-
ter before the interrupt is re-enabled.
Bit
(0x69)
Read/Write
Initial Value
ISC31
R/W
will generate an interrupt. Shorter pulses are not guaranteed to generate an
7
0
ISC30
R/W
6
0
ISC21
R/W
5
0
Table 13-1 on page
”EICRA – External Interrupt Control Register A” on page
25.
ISC20
R/W
4
0
ISC11
ATmega16HVB/32HVB
R/W
3
0
59. Edges on INT3..INT0 are registered
ISC10
R/W
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
Table 32-
EICRA
”Clock
58