ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 127
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.6.3
8042B–AVR–06/10
BGCSR – Bandgap control and Status Register
Figure 21-2.
•
These bits are reserved and will always read as zero.
•
Setting this bit to one will disable the bandgap voltage reference. This bit must be cleared (zero)
before enabling Cell Balancing, CC-ADC, V-ADC or Battery Protection, and must remain unset
(zero) while either of these modules are enabled. Note that after clearing this bit, a settling time
is required before the voltage is stable, see
•
Setting this bit to one will enable the bandgap Short Circuit Detector. This bit should be cleared if
the BGD bit in the BGCSR is set to one to avoid false setting of the BGSCDIF bit.
•
These bits are reserved and will always read as zero.
•
The bit is set when the Bandgap Short Circuit Detector is enabled and buffered bandgap refer-
ence is different from the unbuffered Bandgap reference. The BGSCDIF is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, BGSCDIF is cleared
by writing a logic one to its bit position.
Bit
(0xD2)
Read/Write
Initial Value
Bits 7:6 – Reserved
Bit 5 – BGD: Bandgap Disable
Bit 4 – BGSCDE: Bandgap Short Circuit Detection Enabled
Bits 3:2 – Reserved
Bit 1 – BGSCDIF: Bandgap Short Circuit Detection Interrupt Flag
R
7
–
0
R
6
–
0
BGD
R/W
5
0
BGSCDE
R/W
4
0
”Bandgap Buffer Settling Time” on page
ATmega16HVB/32HVB
R
3
–
0
R
2
–
0
BGSCDIF
R/W
1
0
BGSCDIE
R/W
0
0
124.
BGCSR
127
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