ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 13

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
7.5.1
8042B–AVR–06/10
Stack Pointer
SPH and SPL – Stack Pointer High and Stack Pointer Low
Figure 7-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
X-register
Y-register
Z-register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
RAM-
RAM-
SP15
The X-, Y-, and Z-registers
END
END
SP7
R/W
R/W
15
7
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
SP14
RAM-
RAM-
END
END
SP6
R/W
R/W
14
6
RAM-
RAM-
SP13
R/W
END
END
SP5
R/W
13
5
XH
YH
ZH
0
RAM-
RAM-
SP12
END
END
SP4
R/W
R/W
12
4
ATmega16HVB/32HVB
SP11
RAM-
RAM-
END
END
R/W
R/W
SP3
11
3
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
RAM-
RAM-
SP10
END
END
SP2
R/W
R/W
10
2
RAM-
RAM-
END
END
SP9
SP1
R/W
R/W
9
1
XL
YL
ZL
0
RAM-
RAM-
END
END
R/W
R/W
SP8
SP0
8
0
SPH
SPL
13
0
0
0
0
0