ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 181

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27-6.
27.7.6
27.8
8042B–AVR–06/10
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
Multi-master Systems and Arbitration
Combining Several TWI Modes
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous States
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomic operation. If this principle is violated in a multi-master sys-
tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the
master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 27-19. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a slave receiver.
S
S = START
To/from TWDR
No TWDR action
No TWDR action
Transmitted from master to slave
SLA+W
Application Software Response
A
STA
Master Transmitter
0
ADDRESS
STO
No TWCR action
1
To TWCR
TWINT
1
A
Rs = REPEATED START
Rs
Transmitted from slave to master
TWEA
X
ATmega16HVB/32HVB
SLA+R
Next Action Taken by TWI Hardware
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
A
Master Receiver
DATA
P = STOP
A
P
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