ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 72

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.6
15.3
8042B–AVR–06/10
Alternate Port Functions
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, float-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V
accidentally configured as an output.
Many low voltage port pins have alternate functions in addition to being general digital I/Os.
ure 15-5
be overridden by alternate functions. The overriding signals may not be present in all port pins,
but the figure serves as a generic description applicable to all port pins in the AVR microcon-
troller family.
Figure 15-5. Alternate Port Functions
PTOExn:
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
Pxn
shows how the port pin control signals from the simplified
CC
Pxn, PORT TOGGLE OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
or GND is not recommended, since this may cause excessive currents if the pin is
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
DIEOExn
(1)
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOVxn
SLEEP
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
clk
DIxn:
AIOxn:
SYNCHRONIZER
WPx:
D
L
I/O
SET
CLR
:
Q
Q
ATmega16HVB/32HVB
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
D
PINxn
CLR
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
Figure 15-2 on page 68
1
0
clk
PUD
WDx
RDx
RRx
DIxn
AIOxn
RPx
I/O
WRx
PTOExn
WPx
Fig-
can
72