ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 80

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2
8042B–AVR–06/10
External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects. See
Figure 16-2. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Note:
Tn
The synchronization logic on the input pins (
clk
I/O
D
LE
ExtClk
Q
Table 16-1 on page 81
Synchronization
< f
D
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
n
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
Tn)
for details.
is shown in
ATmega16HVB/32HVB
clk
D
I/O
Figure
). The latch is transparent in the
Q
Figure 16-2
16-2.
Edge Detector
shows a functional
clk_I/O
Tn_sync
(To Clock
Select Logic)
/2.5.
Tn
). The
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