ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 187

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.10.6
27.10.7
8042B–AVR–06/10
TWAMR – TWI (Slave) Address Mask Register
TWBCSR – TWI Bus Control and Status Register
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
detail.
Figure 27-23. TWI Address Match Logic, Block Diagram
• Bit 0 – Reserved
This bit is an unused in the ATmega16HVB/32HVB, and will always read as zero.
• Bit 7 – TWBCIF: TWI Bus Connect/Disconnect Interrupt Flag
Based on the TWBCIP bit, the TWBCIF bit is set when the TWI bus is connected or discon-
nected
vector. Alternatively, TWBCIF is cleared by writing a logic one to the flag. When the SREG I-bit,
TWBCIE (TWI Bus Connect/Disconnect Interrupt Enable), and TWBCIF are set, the TWI Bus
Connect/Disconnect Interrupt is executed. If both SDA and SCL are high during reset, TWBCIF
will be set after reset. Otherwise TWBCIF will be cleared after reset.
Note:
Bit
(0xBD)
Read/Write
Initial Value
Bit
(0xBE)
Read/Write
Initial Value
(1)
1. The TWEN bit in the TWCR register must be set for the Bus Connect/Disconnect feature to be
. TWBCIF is cleared by hardware when executing the corresponding interrupt handling
TWAMR0
Address
TWAR0
enabled.
Bit 0
TWBCIF
R/W
R/W
7
0
X
7
TWBCIE
R/W
6
0
R/W
Address Bit Comparator 6..1
6
0
R/W
5
0
Address Bit Comparator 0
R
5
–
0
TWAM[6:0]
R
4
–
0
R/W
4
0
Figure 27-23
R
3
–
0
R/W
ATmega16HVB/32HVB
3
0
TWBDT1
R/W
2
0
R/W
shown the address match logic in
2
0
TWBDT0
R/W
1
0
R/W
1
0
TWBCIP
R/W
Address
0
0
R
0
–
0
Match
TWBCSR
TWAMR
187