ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 178

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.7.4
8042B–AVR–06/10
Slave Transmitter Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see
Figure
zero or are masked to zero.
Figure 27-17. Data Transfer in Slave Transmitter Mode
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgment of the device’s own slave address or the general call address. TWSTA and
TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After
its own slave address and the write bit have been received, the TWINT flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in
The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-
fer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver
transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave
mode, and will ignore the master if it continues the transfer. Thus the master receiver receives
all “1” as serial data. State 0xC8 is entered if the master demands additional data bytes (by
transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expect-
ing NACK from the master).
TWCR
SDA
TWAR
SCL
Value
Value
27-17). All the status codes mentioned in this section assume that the prescaler bits are
TRANSMITTER
Device 1
SLAVE
TWINT
TWA6
0
Device 2
RECEIVER
MASTER
TWEA
TWA5
1
TWSTA
TWA4
Device 3
0
Device’s Own Slave Address
TWSTO
TWA3
........
0
ATmega16HVB/32HVB
TWWC
TWA2
Device n
0
V
BUS
TWEN
TWA1
1
R1
TWA0
–
0
R2
Table
TWGCE
TWIE
X
27-5.
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