EVB9311 SMSC, EVB9311 Datasheet - Page 8

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

14.2.3 GPIO/LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
14.2.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.2.5 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.2.6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
14.2.7 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
14.2.8 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
14.2.9 Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
14.3
14.3.1 Host MAC Control Register (HMAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
14.3.2 Host MAC Address High Register (HMAC_ADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.3.3 Host MAC Address Low Register (HMAC_ADDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) . . . . . . . . . . . . . . . . . . . . . . . 277
14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL). . . . . . . . . . . . . . . . . . . . . . . . 278
14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
14.3.8 Host MAC Flow Control Register (HMAC_FLOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Revision 1.7 (06-29-10)
14.2.3.1
14.2.3.2
14.2.3.3
14.2.3.4
14.2.4.1
14.2.4.2
14.2.5.1
14.2.5.2
14.2.5.3
14.2.5.4
14.2.5.5
14.2.5.6
14.2.5.7
14.2.5.8
14.2.5.9
14.2.5.10
14.2.5.11
14.2.5.12
14.2.5.13
14.2.5.14
14.2.5.15
14.2.5.16
14.2.5.17
14.2.5.18
14.2.5.19
14.2.5.20
14.2.5.21
14.2.5.22
14.2.5.23
14.2.5.24
14.2.6.1
14.2.6.2
14.2.6.3
14.2.6.4
14.2.6.5
14.2.6.6
14.2.6.7
14.2.6.8
14.2.7.1
14.2.7.2
14.2.8.1
14.2.8.2
14.2.8.3
14.2.8.4
14.2.8.5
14.2.8.6
14.2.8.7
14.2.8.8
14.2.9.1
14.2.9.2
14.2.9.3
14.2.9.4
14.2.9.5
14.2.9.6
14.2.9.7
14.2.9.8
Host MAC Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
General Purpose I/O Configuration Register (GPIO_CFG) .......................................................................................................................... 193
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) ........................................................................................................... 195
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)...................................................................................... 196
LED Configuration Register (LED_CFG) ...................................................................................................................................................... 197
EEPROM Command Register (E2P_CMD) .................................................................................................................................................. 198
EEPROM Data Register (E2P_DATA).......................................................................................................................................................... 201
Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) .......................................................... 202
Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) .......................................................... 203
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)..... 204
Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)........................................ 205
Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x).......................................................... 206
Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) ......................................................... 207
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) .... 208
Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) ....................................... 209
GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8).................................................................. 210
GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) ................................................................. 211
GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9).................................................................. 212
GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) ................................................................. 213
1588 Clock High-DWORD Register (1588_CLOCK_HI)............................................................................................................................... 214
1588 Clock Low-DWORD Register (1588_CLOCK_LO) .............................................................................................................................. 215
1588 Clock Addend Register (1588_CLOCK_ADDEND) ............................................................................................................................. 216
1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)................................................................................................... 217
1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) .................................................................................................. 218
1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) ..................................................................... 219
1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO).............................................................. 220
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) ................................................................................................ 221
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) ............................................................................................. 222
1588 Configuration Register (1588_CONFIG).............................................................................................................................................. 223
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)................................................................................................................ 227
1588 Command Register (1588_CMD) ........................................................................................................................................................ 229
Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... 230
Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... 232
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) ......................................................................................................... 234
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... 236
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... 237
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ 239
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... 240
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) ................................................................................. 241
PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. 244
PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... 245
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... 247
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... 249
Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... 251
Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ 252
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... 253
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. 255
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... 257
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. 258
Chip ID and Revision (ID_REV).................................................................................................................................................................... 260
Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... 261
Hardware Configuration Register (HW_CFG)............................................................................................................................................... 262
Power Management Control Register (PMT_CTRL) .................................................................................................................................... 264
General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... 267
General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... 268
Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 269
Reset Control Register (RESET_CTL) ......................................................................................................................................................... 270
DATASHEET
8
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
SMSC LAN9311/LAN9311i
Datasheet