EVB9311 SMSC, EVB9311 Datasheet

EVALUATION BOARD LAN9311-NU

EVB9311

Manufacturer Part Number
EVB9311
Description
EVALUATION BOARD LAN9311-NU
Manufacturer
SMSC
Series
0133r
Datasheet

Specifications of EVB9311

Main Purpose
Interface, Ethernet
Embedded
No
Utilized Ic / Part
LAN9311
Primary Attributes
2 Ports, 100BASE-TX/10BASE-T, Managed
Secondary Attributes
2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1076
PRODUCT FEATURES
Highlights
Target Applications
Key Benefits
SMSC LAN9311/LAN9311i
High performance and full featured 2 port switch with
Easily interfaces to most 16-bit embedded CPU’s
Unique Virtual PHY feature simplifies software
Integrated IEEE 1588 Hardware Time Stamp Unit
Cable, satellite, and IP set-top boxes
Digital televisions
Digital video recorders
VoIP/Video phone systems
Home gateways
Test/Measurement equipment
Industrial automation systems
Ethernet Switch Fabric
Switch Management
VLAN, QoS packet prioritization, Rate Limiting, IGMP
monitoring and management functions
development by mimicking the multiple switch ports
as a single port MAC/PHY
— 32K buffer RAM
— 1K entry forwarding table
— Port based IEEE 802.1Q VLAN support (16 groups)
— IEEE 802.1d spanning tree protocol support
— QoS/CoS Packet prioritization
— IGMP v1/v2/v3 monitoring for Multicast packet filtering
— Programmable filter by MAC address
— Port mirroring/monitoring/sniffing: ingress and/or egress
— Fully compliant statistics (MIB) gathering counters
— Control registers configurable on-the-fly
traffic on any ports or port pairs
– Programmable IEEE 802.1Q tag insertion/removal
– 4 dynamic QoS queues per port
– Input priority determined by VLAN tag, DA lookup,
– Programmable class of service map based on input
– Remapping of 802.1Q priority field on per port basis
– Programmable rate limiting at the ingress/egress
TOS, DIFFSERV or port default value
priority
ports with random early discard, per port / priority
DATASHEET
Two Port 10/100 Managed
Ethernet Switch with 16-Bit
Non-PCI CPU Interface
Ports
High-performance host bus interface
IEEE 1588 Hardware Time Stamp Unit
Comprehensive Power Management Features
Other Features
Single 3.3V power supply
Available in Commercial & Industrial Temp. Ranges
— 2 internal 10/100 PHYs with HP Auto-MDIX support
— Fully compliant with IEEE 802.3 standards
— 10BASE-T and 100BASE-TX support
— Full and half duplex support
— Full duplex flow control
— Backpressure (forced collision) half duplex flow control
— Automatic flow control based on programmable levels
— Automatic 32-bit CRC generation and checking
— Automatic payload padding
— 2K Jumbo packet support
— Programmable interframe gap, flow control pause value
— Full transmit/receive statistics
— Auto-negotiation
— Automatic MDI/MDI-X
— Loop-back mode
— Provides in-band network communication path
— Access to management registers
— Simple, SRAM-like interface
— 16-bit data bus
— Big, little, and mixed endian support
— Large TX and RX FIFO’s for high latency applications
— Programmable water marks and threshold levels
— Host interrupt support
— Global 64-bit tunable clock
— Master or slave mode per port
— Time stamp on TX or RX of Sync and Delay_req
— 64-bit timer comparator event generation (GPIO or IRQ)
— Wake on LAN
— Wake on link status change (energy detect)
— Magic packet wakeup
— Wakeup indicator event signal
— General Purpose Timer
— Serial EEPROM interface (I
— Programmable GPIOs/LEDs
LAN9311/LAN9311i
packets per port, Timestamp on GPIO
master) for non-managed configuration
2
C master or Microwire
Revision 1.7 (06-29-10)
Datasheet
TM

Related parts for EVB9311

EVB9311 Summary of contents

Page 1

... Programmable filter by MAC address Switch Management — Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs — Fully compliant statistics (MIB) gathering counters — Control registers configurable on-the-fly SMSC LAN9311/LAN9311i LAN9311/LAN9311i Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Ports — ...

Page 2

... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’ ...

Page 3

... Host MAC Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.5 Host MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.6 Power Management Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SMSC LAN9311/LAN9311i 3 DATASHEET Revision 1.7 (06-29-10) ...

Page 4

... Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.1.1 MII MAC Interface ........................................................................................................................................................................................... 84 7.2.1.2 4B/5B Encoder................................................................................................................................................................................................ 84 7.2.1.3 Scrambler and PISO ....................................................................................................................................................................................... 86 7.2.1.4 NRZI and MLT-3 Encoding ............................................................................................................................................................................. 86 7.2.1.5 100M Transmit Driver ..................................................................................................................................................................................... 86 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 4 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 5

... PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.5.5 PIO Burst Reads 108 8.5.6 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.7 RX Data FIFO Direct PIO Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.8 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5.9 TX Data FIFO Direct PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SMSC LAN9311/LAN9311i 5 DATASHEET Revision 1.7 (06-29-10) ...

Page 6

... ERASE (Erase Location) .............................................................................................................................................................................. 146 10.2.3.3 ERAL (Erase All)........................................................................................................................................................................................... 147 10.2.3.4 EWDS (Erase/Write Disable) ........................................................................................................................................................................ 147 10.2.3.5 EWEN (Erase/Write Enable)......................................................................................................................................................................... 148 10.2.3.6 READ (Read Location) ................................................................................................................................................................................. 148 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 6 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 7

... Host MAC RX Dropped Frames Counter Register (RX_DROP)................................................................................................................... 187 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)............................................................................................................... 188 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) ...................................................................................................................... 189 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG) ...................................................................................................... 190 SMSC LAN9311/LAN9311i 7 DATASHEET Revision 1.7 (06-29-10) ...

Page 8

... Host MAC MII Data Register (HMAC_MII_DATA 280 14.3.8 Host MAC Flow Control Register (HMAC_FLOW 281 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1 283 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 8 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 9

... Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 372 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 373 14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 375 14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 376 SMSC LAN9311/LAN9311i 9 DATASHEET Revision 1.7 (06-29-10) ...

Page 10

... Power-On Configuration Strap Valid Timing 446 15.5.4 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.5.5 PIO Burst Read Cycle Timing 448 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 10 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 11

... TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.5.10 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Chapter 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.2 128-XVTQFP Package Outline 457 Chapter 17 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 SMSC LAN9311/LAN9311i 11 DATASHEET Revision 1.7 (06-29-10) ...

Page 12

... Figure 10.13EEPROM WRAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 10.14EEPROM Loader Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 11.1 IEEE 1588 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 11.2 IEEE 1588 Message Time Stamp Point 157 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 12 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 13

... Figure 15.10Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Figure 16.1 LAN9311 128-VTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Figure 16.2 LAN9311 128-VTQFP Recommended PCB Land Pattern 456 Figure 16.3 LAN9311/LAN9311i 128-XVTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Figure 16.4 LAN9311/LAN9311i 128-XVTQFP Recommended PCB Land Pattern . . . . . . . . . . . . . . . . 458 SMSC LAN9311/LAN9311i 13 DATASHEET Revision 1.7 (06-29-10) ...

Page 14

... Table 13.1 LED Operation as a Function of LED_CFG[9: 165 Table 14.1 System Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 14.2 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 14 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 15

... Table 15.13TX Data FIFO Direct PIO Write Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Table 15.14Microwire Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Table 15.15LAN9311/LAN9311iCrystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Table 16.1 LAN9311 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions 458 Table 17.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 SMSC LAN9311/LAN9311i 15 DATASHEET Revision 1.7 (06-29-10) ...

Page 16

... This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true, and the status bit is cleared by writing a zero. Least Significant Bit Least Significant Byte Medium Dependant Interface Media Independent Interface with Crossover 16 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 17

... SMI SQE SSD UDP UUID WORD SMSC LAN9311/LAN9311i Media Independent Interface Media Independent Interface Management MAC Interface Layer Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. ...

Page 18

... ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power pin Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Chapter 3, "Pin Description and Configuration," Table 1.1 Buffer Types DESCRIPTION 18 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 19

... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9311/LAN9311i Table 1.2 Register Bit Types REGISTER BIT DESCRIPTION ...

Page 20

... IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test and measurement equipment. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 2 C/Microwire master EEPROM controller for connection DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 21

Block Diagram IEEE 1588 Time Stamp MII To Ethernet 10/100 10/100 PHY MAC MDIO Registers IEEE 1588 Time Stamp MII To Ethernet 10/100 10/100 PHY MAC MDIO Registers GPIO/LED Controller LAN9311/LAN9311i To optional GPIOs/LEDs 10/100 MAC IEEE 1588 Search ...

Page 22

... Reset Control Register (RESET_CTL) Reset Control Register (PMT_CTRL), or Reset (bit 15) in the Interrupt Status Register (INT_STS) (INT_EN). These registers aggregate and control all interrupts from the 22 DATASHEET Datasheet or Reset (bit or Reset (bit (RESET_CTL), (bit 10) in Virtual PHY Basic and SMSC LAN9311/LAN9311i ...

Page 23

... HBI interfaces to the switch fabric via the Host MAC, which contains the TX/RX Data and Status FIFOs, Host MAC registers and power management features. The main features of the HBI are: Asynchronous 16-bit Host Bus Interface - Host Data Bus Endianess Control - Direct FIFO Access Modes SMSC LAN9311/LAN9311i Interrupt Configuration Register 23 DATASHEET Revision 1.7 (06-29-10) ...

Page 24

... The Host MAC interfaces to the Switch Engine Port 0 via 2 C/Microwire master module which interfaces an optional external 2 C-Bus Specification. EEPROM Command Register 24 DATASHEET Datasheet Host MAC CSR Interface Command system and Host 2 C/Microwire) and Reset Control Register (RESET_CTL)), (E2P_CMD). SMSC LAN9311/LAN9311i ...

Page 25

... Chapter 8, "Host Bus Interface (HBI)," on page The 2 Ethernet ports of the LAN9311/LAN9311i must be connected to Auto-MDIX style magnetics for proper operation on the Ethernet network. Refer to the SMSC Application Note 8.13 “Suggested Magnetics” for further details. The LAN9311/LAN9311i also supports optional EEPROM and GPIOs/LEDs. When an EEPROM is ...

Page 26

... Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW) Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface SMSC LAN9311 128-VTQFP TOP VIEW 26 DATASHEET Datasheet VDD33IO 64 IRQ 63 62 PME 61 END_SEL 60 FIFO_SEL 59 nCS 58 nWR 57 nRD VDD33IO VSS VDD33IO VDD18CORE 40 VDD33IO VDD33IO SMSC LAN9311/LAN9311i ...

Page 27

... RXP2 123 RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9311/LAN9311i SMSC LAN9311/LAN9311i 128-XVTQFP TOP VIEW VSS NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND 27 DATASHEET VDD33IO 64 63 IRQ PME ...

Page 28

... LED Configuration Register General Purpose I/O Configuration and General Purpose I/O (GPIO_DATA_DIR). The See Chapter 13, "GPIO/LED Controller," on page 163 for additional details. Note 3.1 for additional Note 3.1 for additional Note 3.1 for additional Note 3.1 for additional SMSC LAN9311/LAN9311i ...

Page 29

... PIN NAME Bias 119 Reference +3.3V Port 1 Analog Power 114,117 Supply SMSC LAN9311/LAN9311i Table 3.2 LAN Port 2 Pins BUFFER SYMBOL TYPE OD12 LED indicators: When configured as LED outputs via the LED Configuration Register these pins are open-drain, active low outputs and the pull-ups and input buffers are disabled ...

Page 30

... This signal is qualified by the nCS chip select. nCS IS Chip Select: Active low signal used to qualify read and write operations. 30 DATASHEET Datasheet DESCRIPTION DESCRIPTION Big and little endianess is supported. The A0 bit is not used because the LAN9311/LAN9311i must be accessed on WORD boundaries. SMSC LAN9311/LAN9311i ...

Page 31

... Input/Output EEPROM Microwire Data Output 98 EEPROM EEPROM_TYPE Type Strap SMSC LAN9311/LAN9311i BUFFER SYMBOL TYPE IS Data FIFO Direct Access Select: When driven high, all accesses to the LAN9311/LAN9311i are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO ...

Page 32

... EEPROM and is recommended if no EEPROM is attached. Section 2 138. This bit is not used for I C Note 3. mode (EEPROM_TYPE=1), this pin is not used and is driven low. Section 138. See Note 3.4. Section 15.5.2, "Reset and Section 15.5.2, "Reset and 2 C mode. SMSC LAN9311/LAN9311i Section ...

Page 33

... Note 3.6 Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap pins are identified by an underlined symbol name. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to "Configuration Straps," on page 40 SMSC LAN9311/LAN9311i BUFFER SYMBOL TYPE LED_EN ...

Page 34

... Table 3.1 and Table 3.2. Interrupt Configuration (IRQ_CFG). For more information, refer to 49. Section The LAN9311/LAN9311i must always be read at least once after power-up or reset to ensure that write operations function properly. Chapter 4, "Clocking, Resets, and Power for additional SMSC LAN9311/LAN9311i 163. ...

Page 35

... PIN NAME 1,2, 4-6, No Connect 8-12, 15-17,19, 20,22-24, 76,94,95, 102,103, 109 SMSC LAN9311/LAN9311i Table 3.8 PLL Pins BUFFER SYMBOL TYPE P PLL +1.8V Power Supply: This pin must be connected to VDD18CORE for proper operation. Refer to the LAN9311/LAN9311i application note for additional connection information. ...

Page 36

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for additional details. Table 15.15, “LAN9311/LAN9311iCrystal Specifications,” Section 4.2.4, "Configuration Straps," on page 40 Section 10.2.4, "EEPROM Loader," on page 150 36 DATASHEET Datasheet Section 15.6, "Clock Circuit," on Chapter 12, "General Purpose for for additional SMSC LAN9311/LAN9311i ...

Page 37

... READY bit is cleared. Writes to any address are invalid until the READY bit is set. Note: The LAN9311/LAN9311i must be read at least once after any chip-level reset to ensure that write operations function properly. SMSC LAN9311/LAN9311i ...

Page 38

... DATASHEET Datasheet 2 C, 28uS for 2 C EEPROM, and 445. Configuration straps 2 C, 28uS for 2 C EEPROM, and for a description of the nRST pin. Hardware until it is set. Power Management Control Reset Control Register Reset Control Register 2 C, 28uS for SMSC LAN9311/LAN9311i ...

Page 39

... PHY registers. Refer to information. Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the Register (RESET _CTL) SMSC LAN9311/LAN9311i Hardware Configuration Register Port x PHY Basic Control Register Section 7.2.9, "PHY Power-Down Modes," on page 94 or the Reset bit in the Port x PHY Basic Control Register until it clears ...

Page 40

... Reset Control Register (RESET_CTL) EEPROM Command Register 40 DATASHEET Datasheet Reset Control Register (PMT_CTRL), or Reset in Reset Control (PMT_CTRL), until it clears. Under for additional information on Virtual PHY Chapter 3, "Pin Description and for information or upon issuing a (E2P_CMD), these straps return to their SMSC LAN9311/LAN9311i 445. ...

Page 41

... Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9311/LAN9311i LED Configuration Register One pin configures the default for all 8 LED/GPIOs, but 8 separate bits are loaded by the EEPROM Loader, allowing individual control over each LED/GPIO ...

Page 42

... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 1 Backpressure Enable bit of the Port 1 Manual Flow Control Register Port 1 Full-Duplex and (MANUAL_FC_1), 42 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 1 Full- bits in the SMSC LAN9311/LAN9311i ...

Page 43

... Full Duplex (bit 6) and 10BASE-T Half Duplex (bit 5) bits of the Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9311/LAN9311i Port 1 Full-Duplex Manual Flow Control bit in the Port 1 Manual Flow (MANUAL_FC_1). When configured low, is set). and ...

Page 44

... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register Port 2 Full-Duplex and (MANUAL_FC_2), 44 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 2 Full- bits in the SMSC LAN9311/LAN9311i ...

Page 45

... These straps, along with their pin assignments are also fully defined in Chapter 3, "Pin Description and Configuration," on page SMSC LAN9311/LAN9311i Port 2 Full-Duplex Manual Flow Control bit in the Port 2 Manual Flow (MANUAL_FC_2) ...

Page 46

... Section 10.2, "I2C/Microwire Master 138. Section 7.1.1, "PHY Addressing," on page (INT_STS). The PME_INT status bit is then masked with the PME_EN bit and (PMT_CTRL). These bits allow the PME to be open-drain, 46 DATASHEET Datasheet PIN EEPROM_TYPE EEPROM_SIZE_[1:0] PHY_ADDR_SEL 82. Power Management Control Register SMSC LAN9311/LAN9311i ...

Page 47

... IRQ interrupt output pin, as described in on page 52. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 95 operation and configuration of the PHY energy-detect power-down mode. SMSC LAN9311/LAN9311i WOL_EN (bit 9) of PMT_CTRL register WOL_STS (bit 5) of PMT_CTRL register ED_EN1 (bit 14) of ...

Page 48

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (PMT_CTRL). Power Management Control Register (PMT_CTRL) (PMT_CTRL). 53. for additional details on these features. 48 DATASHEET Datasheet Power Host (via the WUEN bit for wake-up frames, will be set. These Power Section and Section 9.5.1, "Magic Packet SMSC LAN9311/LAN9311i ...

Page 49

... IRQ pin de-asserts, regardless of the reason. Note: The de-assertion timer does not apply to the PME interrupt. Assertion of the PME interrupt does not affect the de-assertion timer. SMSC LAN9311/LAN9311i (Port 2,1,0 and GPIO 9,8) (Buffer Manager, Switch Engine, and Port 2,1,0 MACs) ...

Page 50

... SWE_IMR of SW_IPR register SWE_IPR Port [2,1,0] MAC Interrupt Registers Bits [2,1,0] (MAC_[2,1,MII]) MAC_IMR_[2,1,MII] of SW_IPR register MAC_IPR_[2,1,MII] Port 2 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_2 PHY_INTERRUPT_MASK_2 Port 1 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 Power Management Control Register PMT_CTRL GPIO Interrupt Register GPIO_INT_STS_EN 50 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 51

... IRQ output must be enabled via bit 8 (IRQ_EN) of the For additional details on the Switch Fabric interrupts, refer to on page 81. SMSC LAN9311/LAN9311i for bit-level definitions of all interrupt registers. Interrupt Status Register (INT_STS) 1588 Interrupt Status and Enable Register 1588 Interrupt Status and Enable Register ...

Page 52

... General Purpose I/O Interrupt Stat us and Enable Regist er Interrupt Enable Register (INT_EN) Interrupt Configuration Register Section 13.2.2, "GPIO Interrupts," on page (INT_STS), and Interrupt Enable Register (INT_EN) 52 DATASHEET Datasheet provides indication that a Port x PHY Interrupt Mask General provides enabling/disabling must be set, and (IRQ_CFG). 164. provide the SMSC LAN9311/LAN9311i ...

Page 53

... For additional details on the General Purpose Timer, refer to on page 162. SMSC LAN9311/LAN9311i Interrupt Enable Register Interrupt Configuration Register and Interrupt Status Register (INT_STS) Power Management Control Register provides enabling/disabling and status of all Section 4.3, " ...

Page 54

... Interrupt Status Register (INT_STS) Interrupt Status Register (INT_STS) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the (IRQ_CFG). 54 DATASHEET Datasheet Interrupt Status Register (INT_STS) Interrupt Status Register is set. and Interrupt Interrupt Status Register (INT_STS) will clear it. Interrupt SMSC LAN9311/LAN9311i ...

Page 55

... Status Registers," on page For detailed descriptions of all switch fabric related registers, refer to Descriptions," on page SMSC LAN9311/LAN9311i - These registers provide access to various switch fabric parameters for - A total of three MACs are included in the switch fabric which provide basic - This block is the core of the switch fabric and provides VLAN layer 2 - This block provides control of the free buffer space, transmit queues, and Section 14.2.6, " ...

Page 56

... Table 8.1, “Read After Write Timing Rules,” on page 103 56 DATASHEET Datasheet for writing sequential register Switch Fabric address range automatically set Switch Fabric address range, a sub-set of the Table 14.3, “Switch Fabric CSR to 241. are required where SMSC LAN9311/LAN9311i ...

Page 57

... The user should clear the AUTO_INC and AUTO_DEC bits before reading the last data to avoid an unintended read cycle. Figure 6.2 illustrates the process required to perform a switch fabric CSR read. The minimum wait periods as specified in noted. SMSC LAN9311/LAN9311i CSR Write Auto Increment / Decrement Idle Write ...

Page 58

... CSR_BUSY = 0 CSR_BUSY = 0 last data? Register Yes Write Command Register Read Data Register (MANUAL_FC_MII)). Table 6.1 58 DATASHEET Datasheet min wait period CSR_BUSY = 1 Read Data No Register (Port 1 Manual Flow Control Register (MANUAL_FC_2), or Port 0(Host MAC) details the switch fabric flow control SMSC LAN9311/LAN9311i ...

Page 59

... Advertisement Register (VPHY_AN_ADV) Base Page Ability Register "Virtual PHY Auto-Negotiation," on page 96 SMSC LAN9311/LAN9311i Port x PHY Auto-Negotiation Advertisement Register an d Virtual PHY egotia tio n Advertisement Register are not affected by the values of the manual flow control register. Refer to ...

Page 60

... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 60 DATASHEET Datasheet Section 6.2.3, SMSC LAN9311/LAN9311i ...

Page 61

... Total alignment errors Total bytes received from all packets Total bytes received from good packets Total packets with a symbol error Total MAC control packets SMSC LAN9311/LAN9311i 58. Pause frames are consumed by the MAC and not sent to (MAC_RX_CFG_x). (Section 14.5.2.3, on page 326) (Section 14.5.2.4, on page (Section 14 ...

Page 62

... DATASHEET Datasheet Port x MAC Table 14.12, “Indirectly and Section 14.5.2.25 through 351) 352) 353) 354) 355) 356) 358) SMSC LAN9311/LAN9311i ...

Page 63

... Bit Age / Valid Static Filter Override SMSC LAN9311/LAN9311i (Section 14.5.2.37, on page 360) (Section 14.5.2.38, on page (Section 14.5.2.39, on page (Section 14.5.2.40, on page (Section 14.5.2.41, on page (Section 14.5.2.42, on page 365) Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) ...

Page 64

... Register (SWE_ALR_WR_DAT_1). Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (SWE_PORT_INGRSS_CFG). for additional details Switch Engine ALR Command Register (SWE_ALR_WR_DAT_0), and 64 DATASHEET Datasheet Switch Engine Port (SWE_ALR_CMD_STS), Switch Switch Engine ALR Write Data 1 SMSC LAN9311/LAN9311i ...

Page 65

... Switch Engine ALR Command Register (SWE_ALR_CMD) Next Entry bit step 3. Note: Refer to Section 14.5.3.1, on page 368 definitions of these registers. SMSC LAN9311/LAN9311i with the desired MAC address and control Switch Engine ALR Command Status Register until it is cleared. Switch Engine ALR Command Register (SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1 Register until either are set ...

Page 66

... Enable Membership Checking is set. A NULL membership will also result in the packet being filtered if the destination address is not found in the ALR table (since the packet would have no destinations). Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface is in effect effect). 66 DATASHEET Datasheet Spanning Tree Spanning Tree SMSC LAN9311/LAN9311i ...

Page 67

... Source Port port default table programmable Priority 3b VLAN Priority Regeneration table per port 2b ALR Priority Figure 6.4 Switch Engine Transmit Queue Selection SMSC LAN9311/LAN9311i ALR Static Bit 3b DA Highest Priority programmable priority Traffic Class 3b calculation table 3b 67 DATASHEET Figure 6.4, the priority may ...

Page 68

... Resolved Priority = Resolved Priority = Default Priority[Source DIFFSERV[TOS] DIFFSERV[TC] Traffic Class[Resolved Priority] Get Queue Done 68 DATASHEET Datasheet Get Queue Highest N Priority Y ALR Static Bit N VL Higher Priority Y Y Packet is Tagged N & Use Packet is Tagged N Resolved Priority = Priority Regen[VLAN Port] Priority] Queue = SMSC LAN9311/LAN9311i ...

Page 69

... VLAN Priority Regeneration Table Register 2 Ingress VLAN Priority Regeneration Table Register Section 14.5.3.33, on page 403 these registers. SMSC LAN9311/LAN9311i 6.5, the default priority is based on the ingress ports priority bits in its port VID Switch Engine VLAN Write Data Register (SWE_VLAN_RD_DATA), and Section 14.5.3.8, on page 377 for detailed VLAN register descriptions ...

Page 70

... The host CPU should discard received packets from this port when in the Disabled state. Note: There is no hardware distinction between the Blocking and Disabled states. 70 DATASHEET Datasheet ... 11 0 VID for detailed VLAN (Section (Section 6.4.10, on page 75). is used to place a port into one of the Software Action SMSC LAN9311/LAN9311i ...

Page 71

... EBS. The CIR rate is specified in time per byte. The value programmed is in approximately 20 nS per byte increments. Typical values are listed in receiving at 10Mbps, any setting faster than 39 has the effect of not limiting the rate. SMSC LAN9311/LAN9311i The MAC Address Table should be programmed with entries that the host CPU needs to receive (e ...

Page 72

... Section 14.5.3.29, on page 399 Figure 6.7, the priority can be based on: 72 DATASHEET Datasheet Bandwidth 100 Mbps 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 2.5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps for detailed register SMSC LAN9311/LAN9311i ...

Page 73

... The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6.8. Y Use Precedence Flow Priority = IP Precedence Figure 6.8 Switch Engine Ingress Flow Priority Calculation SMSC LAN9311/LAN9311i Packet is IPv 4 Packet is IP Use Precedence Use IP VLAN Enable Programmable 3b DIFFSERV Table ...

Page 74

... Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) Switch Engine Global Ingress Configuration 64. The host software should also forward the original Switch Engine Global Ingress Configuration Register 74 DATASHEET Datasheet Bandwidth 75 Mbps 50 Mbps 40 Mbps 20 Mbps 10 Mbps 5 Mbps 2.4 Mbps 1.2 Mbps 900 Kbps 600 Kbps 300 Kbps SMSC LAN9311/LAN9311i ...

Page 75

... Such a packet will be filtered if Admit Only VLAN is set on the host CPU port. Either avoid setting Admit Only VLAN on the host CPU port or set an unused bit in the VID field. SMSC LAN9311/LAN9311i Switch Engine Port Mirroring Register are used to enable a special VLAN tag that is ...

Page 76

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface of Port 0 should be set. in the Host MAC should be set to 8100h and the should be set to a value other than 8100h. This configuration 76 DATASHEET Datasheet Port x MAC Receive configures the switch to Host MAC VLAN2 Tag Host MAC VLAN1 SMSC LAN9311/LAN9311i ...

Page 77

... When a packet is read from the memory and sent out to the corresponding port, the used buffers are released. SMSC LAN9311/LAN9311i Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, " ...

Page 78

... Mbps 80 Mbps 65 Mbps 67 Mbps 56 Mbps 57 Mbps 49 Mbps 50 Mbps 39 Mbps 40 Mbps 30 Mbps 31 Mbps 20 Mbps 20 Mbps 10 Mbps 10 Mbps 5 Mbps 5 Mbps 2.5 Mbps 2.5 Mbps 990 Kbps 1 Mbps 490 Kbps 500 Kbps 250 Kbps 250 Kbps 98 Kbps 100 Kbps 49 Kbps 50 Kbps SMSC LAN9311/LAN9311i ...

Page 79

... Priority field of the new VLAN is changed to the egress ports default priority. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9311/LAN9311i Section 6.4.10, "Host CPU Port Special Tagging," on page Buffer Manager Egress Port Type Register must be set ...

Page 80

... VID = Default VID VID = Default VID [ingress_port] [ingress_port] Priority = Default Priority Priority = Unchanged [ingress_port Change Priority Y N [egress_port] Modify Tag VID = Unchanged Priority = Default Priority Send Packet Untouched [egress_port] 80 DATASHEET Datasheet Special Tagged Strip Tag Strip Tag Strip Tag SMSC LAN9311/LAN9311i ...

Page 81

... Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) 6.6 Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page 51. SMSC LAN9311/LAN9311i Section 5.2.2, "Switch Fabric Interrupts," DATASHEET Revision 1.7 (06-29-10) ...

Page 82

... Ethernet PHY registers. Table 7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can PHY Address (PHYADD) field in the 40. PORT 1 PHY DEFAULT ADDRESS VALUE DATASHEET Datasheet Section 14.4, Port x PHY Special Modes Register Section 4.2.4, PORT 2 PHY DEFAULT ADDRESS VALUE SMSC LAN9311/LAN9311i ...

Page 83

... MII MII To Port x MAC Switch Fabric MAC Interface PHY Management MDIO Control To Host MAC Registers Interrupts To System Interrupt Controller SMSC LAN9311/LAN9311i and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs To GPIO/LED Controller Figure 7.1 Port x PHY Block Diagram ...

Page 84

... Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M MLT-3 MLT-3 TX Driver MLT-3 CAT-5 Section 7.2.7, "MII MAC 84 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Interface". Table 7.2. Each 4-bit data-nibble SMSC LAN9311/LAN9311i ...

Page 85

... MII Receive Data Valid (RXDV) 00000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) SMSC LAN9311/LAN9311i Table 7.2 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 ...

Page 86

... MHz logic and the 100BASE-TX Transmitter. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 86 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID Section 7.1.1, "PHY SMSC LAN9311/LAN9311i ...

Page 87

... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN9311/LAN9311i Figure 7.3. Shaded blocks are those which are internal ...

Page 88

... Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 88 DATASHEET Datasheet Section 7.2.7, "MII MAC SMSC LAN9311/LAN9311i ...

Page 89

... The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in SMSC LAN9311/LAN9311i Section 7.2.7, "MII MAC Port x PHY Special Control/Status Indication Register ...

Page 90

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port x PHY Auto-Negotiation Advertisement for additional details on how to use the LAN9311/LAN9311i Port x PHY Special Control/Status Port x PHY Auto-Negotiation Link (PHY_AN_LP_BASE_ABILITY_x). 90 DATASHEET Datasheet Section 7.2.7, "MII MAC Port x PHY Basic Section 14.4.2.5, "Port x 295. Refer to Section SMSC LAN9311/LAN9311i ...

Page 91

... Advertisement Register (PHY_AN_ADV_x) x PHY Basic Control Register will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the PHY Basic Control Register SMSC LAN9311/LAN9311i Reset Control Register (RESET_CTL), or bit 15 of the (Section 7.2.9, "PHY Power-Down Modes," on page Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ...

Page 92

... Port x PHY Basic Control Register Port x PHY Basic Control Register Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) 92 DATASHEET Datasheet Port 1 are not affected by the Port x PHY Auto-Negotiation Port x PHY Auto-Negotiation Port x PHY Basic Control Register Port x PHY Basic Control (PHY_BASIC_CONTROL_x). The should SMSC LAN9311/LAN9311i ...

Page 93

... The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3. SMSC LAN9311/LAN9311i Figure 7.4 (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is Section 3.2, " ...

Page 94

... PHY interrupt. The PHY Management Control Interrupt Status Register (INT_STS) Chapter 5, "System Interrupts," on page Table 7.3 PHY Interrupt Sources PHY_INTERRUPT_MASK_x & PHY_INTERRUPT_SOURCE_x REGISTER BIT # 46. 94 DATASHEET Datasheet Table 7.3. Reading shows the source of bit 26 (PHY_INT1) for 49 SMSC LAN9311/LAN9311i ...

Page 95

... Port 2 PHY is reset by setting bit 2 (PHY2_RST). These bits are self clearing after approximately 102uS. This reset does not reload the configuration strap values into the PHY registers. SMSC LAN9311/LAN9311i (PHY_MODE_CONTROL_STATUS_x). When in this mode energy is Port x PHY Mode Control/Status Register ...

Page 96

... Required Ethernet Magnetics The magnetics selected for use with the LAN9311/LAN9311i should be an Auto-MDIX style magnetic, which is widely available from several vendors. Please review the SMSC Application note 8.13 “Suggested Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are provided within the application note ...

Page 97

... Disabling Auto-Negotiation Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Basic Control Register to reflect the speed (bit 13) and duplex (bit 8) of the SMSC LAN9311/LAN9311i Virtual PHY Auto-Negotiation Expansion Register Parallel Detection is used. are set to indicate the emulated link partners abilities. ...

Page 98

... Virtual PHY Basic Control Register (VPHY_AN_ADV). This allows the Section 14.2.8.5, "Virtual PHY 253. Virtual PHY Auto-Negotiation Table 14.5, 256. Port 0(Host MAC) Manual Flow are not Section 6.2.3, "Flow Control Enable 36. by setting bit 3 Virtual PHY Basic Control by setting bit SMSC LAN9311/LAN9311i ...

Page 99

... WORD forming a 32-bit transaction with no cycles to the LAN9311/LAN9311i in between. With the exception of A[1], all address and control signals must be the same for both 16-bit cycles of a 32-bit transaction. SMSC LAN9311/LAN9311i Chapter 9, "Host MAC," on page 113 Chapter 5, "System Interrupts," on page Table 3 ...

Page 100

... Data path operations for the supported endian configurations are illustrated in Figure 8.1, "Little Endian Byte Ordering" and Figure 8.2, "Big Endian Byte Ordering". Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 100 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 101

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet . SMSC LAN9311/LAN9311i 16-BIT LITTLE ENDIAN (END_SEL = 0) INTERNAL ORDER MSB A[ A[ HOST DATA BUS Figure 8.1 Little Endian Byte Ordering 16-BIT BIG ENDIAN (END_SEL = 1) INTERNAL ORDER MSB A[ A[ HOST DATA BUS Figure 8 ...

Page 102

... Table 8.1. The host processor is required to wait the Byte Order Test Register (BYTE_TEST) (45ns). For microprocessors with slower cyc 102 DATASHEET Datasheet Section 15.5, "AC TX FIFO Information Register register is a convenient way Table 8.1 shows the number of SMSC LAN9311/LAN9311i ...

Page 103

... FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPT_CFG GPT_CNT FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG 1588_CLOCK_HI_RX_CAPTURE_1 1588_CLOCK_LO_RX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 1588_SRC_UUID_LO_RX_CAPTURE_1 1588_CLOCK_HI_TX_CAPTURE_1 1588_CLOCK_LO_TX_CAPTURE_1 SMSC LAN9311/LAN9311i Table 8.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS 135 ...

Page 104

... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING 104 DATASHEET Datasheet NUMBER OF BYTE_TEST READS OF 45NS) CYC SMSC LAN9311/LAN9311i ...

Page 105

... Table 8.1 Read After Write Timing Rules (continued) REGISTER NAME 1588_CONFIG 1588_INT_STS_EN MANUAL_FC_1 MANUAL_FC_2 MANUAL_FC_MII SWITCH_CSR_DATA SWITCH_CSR_CMD E2P_CMD E2P_DATA LED_CFG VPHY_BASIC_CTRL VPHY_BASIC_STATUS VPHY_ID_MSB VPHY_ID_LSB VPHY_AN_ADV VPHY_AN_LP_BASE_ABILITY VPHY_AN_EXP VPHY_SPECIAL_CONTROL_STATUS GPIO_CFG GPIO_DATA_DIR GPIO_INT_STS_EN SWITCH_MAC_ADDRH SWITCH_MAC_ADDRL RESET_CTL SWITCH_CSR_DIRECT_DATA SMSC LAN9311/LAN9311i MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING ...

Page 106

... Table 8.2 Read After Read Timing Rules OR PERFORM THIS MANY READS OF BYTE_TEST… (ASSUMING T CYC 135 3 135 3 135 3 180 106 DATASHEET Datasheet register is a convenient way Table 8.2 below also shows the number of OF 45NS) BEFORE READING... RX_FIFO_INF RX_FIFO_INF TX_FIFO_INF RX_DROP SWITCH_CSR_CMD Note 8.1 VPHY_AN_EXP SMSC LAN9311/LAN9311i ...

Page 107

... Note: Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer to Section 8.5.2 END_SEL A[x:1] nCS, nRD D[15:0] (OUTPUT) Figure 8.3 Functional Timing for PIO Read Operation SMSC LAN9311/LAN9311i Table 15.8, “PIO Read Cycle Timing Values,” on page for information on these restrictions. VALID VALID 107 DATASHEET 447. The cycle ends when Figure 8 ...

Page 108

... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 15.9, “PIO Burst Read Cycle Timing Values,” on VALID VALID VALID VALID VALID VALID VALID 108 DATASHEET Datasheet for the AC timing VALID VALID VALID SMSC LAN9311/LAN9311i ...

Page 109

... AC timing specifications for RX Data FIFO direct PIO read operations. FIFO_SEL END_SEL A[x:3] A[2:1] nCS, nRD D[15:0] (OUTPUT) Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation SMSC LAN9311/LAN9311i VALID VALID VALID (READ DATA FROM RX DATA FIFO) 109 DATASHEET 449. ...

Page 110

... Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 450. The burst cycle ends when Figure 110 DATASHEET Datasheet Table 15.11, 8.6. for SMSC LAN9311/LAN9311i ...

Page 111

... Section 15.5.8, "PIO Write Cycle Timing," on page 451 for PIO write operations. END_SEL A[x:1] nCS, nWR D[15:0] (INPUT) Figure 8.7 Functional Timing for PIO Write Operation SMSC LAN9311/LAN9311i Table 15.12, “PIO Write Cycle Timing Figure 8.7. for the AC timing specifications VALID VALID ...

Page 112

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface VALID VALID (WRITE DATA TO TX DATA FIFO) Interrupt Status Register (INT_STS), and 112 DATASHEET Datasheet 452. The cycle for the AC VALID Interrupt Configuration Interrupt Enable Register (INT_EN) Chapter 5, System Interrupts. SMSC LAN9311/LAN9311i at ...

Page 113

... Flow control during full-duplex mode Decoding of control frames (PAUSE command) and disabling the transmitter Generation of control frames Interface between the Host Bus Interface and the Ethernet PHYs/Switch Fabric. SMSC LAN9311/LAN9311i system registers. Configuration". This depth of buffer storage minimizes or Host MAC MII Access Register (HMAC_MII_ACC) (HMAC_MII_DATA) ...

Page 114

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Host MAC Automatic Flow Control Configuration Register (AFC_CFG) Host MAC Flow Control Register (HMAC_FLOW) and Host MAC VLAN2 Tag Register 114 DATASHEET Datasheet located located in the Figure 9.1, Host (HMAC_VLAN2), SMSC LAN9311/LAN9311i ...

Page 115

... Note: This filtering function is performed after any switch fabric filtering functions. The user must ensure the switch filtering is setup properly to allow packets to be passed to the Host MAC for further filtering. SMSC LAN9311/LAN9311i Standard Ethernet Frame (1518 Bytes) Source Addr. Type ...

Page 116

... Hash Filtering for physical and multicast addresses Inverse Filtering Promiscuous Pass all multicast frames. Frames with physical addresses are perfect-filtered Pass all multicast frames. Frames with physical addresses are hash- filtered and the Host MAC to form a Host MAC (HMAC_ADDRL). SMSC LAN9311/LAN9311i ...

Page 117

... Note: When wake-up frame detection is enabled via the WUEN bit of the and Status Register despite the state of the Disable Broadcast Frames (BCAST) bit in the Register (HMAC_CR). SMSC LAN9311/LAN9311i and the Host MAC Address Low Register Host MAC Control Register (HMAC_CR) Host MAC Wake-up Control and Status Register (HMAC_WUFF) ...

Page 118

... Filter 2 Offset Filter 1Offset Table 9.3, describes the byte mask’s bit fields. FILTER I BYTE MASK DESCRIPTION Table 9.4 FILTER i COMMANDS 118 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter i command register. SMSC LAN9311/LAN9311i ...

Page 119

... Host MAC address. For example, if the Host MAC address is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet frame: SMSC LAN9311/LAN9311i Table 9.5 describes the Filter i Offset bit fields. ...

Page 120

... Switch Fabric MAC Address Low Register and Switch Fabric MAC Address High Register Register Locations Written HMAC_ADDRL[7:0] SWITCH_MAC_ADDRL[7:0] HMAC_ADDRL[15:8] SWITCH_MAC_ADDRL[15:8] HMAC_ADDRL[23:16] SWITCH_MAC_ADDRL[23:16] HMAC_ADDRL[31:24] SWITCH_MAC_ADDRL[31:24] HMAC_ADDRH[7:0] SWITCH_MAC_ADDRH[7:0] HMAC_ADDRH[15:8] SWITCH_MAC_ADDRH[15:8] 120 DATASHEET Datasheet and (SWITCH_MAC_ADDRH). Order of Reception on Ethernet Figure 9.2. The values required to SMSC LAN9311/LAN9311i ...

Page 121

... MIL FIFOs, the host no longer can control or access the data. The MIL FIFOs are essentially the working buffers of the Host MAC logic. In the case of reception, the data must be moved into the RX FIFOs before the host can access the data. For TX SMSC LAN9311/LAN9311i 23 16 ...

Page 122

... The TX_FIF_SZ field selects the total allocation for the TX data Table 9.8 TX/RX FIFO Configurable Sizes SIZE RANGE 512 128-892 1536-13824 1920-13440 122 DATASHEET Datasheet Host MAC RX Dropped Frames Counter (HW_CFG). The field in the Hardware Table 9.9 DEFAULT 512 704 4608 10560 SMSC LAN9311/LAN9311i shows ...

Page 123

... DWORDs of the buffer. Data before the “Data Start Offset” pointer will be ignored. When a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. SMSC LAN9311/LAN9311i Table 9.9 Valid TX/RX FIFO Allocations TX STATUS FIFO ...

Page 124

... DWORDs are stored in the TX Status FIFO to be read by the host at a later time upon completion of the data transmission onto the wire. Figure 9.3 Simplified Host TX Flow Diagram Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface TX FIFO Information Register 124 DATASHEET Datasheet (TX_FIFO_INF). The SMSC LAN9311/LAN9311i ...

Page 125

... There is a 16-bit Packet Tag in the TX command ‘B’ command word. Packet Tags may, if host software desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned in the TX status word for the associated packet. The Packet tag can be used by host software to uniquely identify each status word returned to the host. SMSC LAN9311/LAN9311i 31 Order TX Command 'A' ...

Page 126

... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 9.10 TX Command 'A' Format DESCRIPTION [25] [24] End Alignment 0 0 4-byte alignment 0 1 16-byte alignment 1 0 32-byte alignment 1 1 Reserved 126 DATASHEET Datasheet Interrupt Status SMSC LAN9311/LAN9311i ...

Page 127

... The final buffer of any transmit packet can be any length The MIL operates in store-and-forward mode and has specific rules with respect to fragmented packets. The total space consumed in the TX MIL FIFO must be limited to no more than 2KB - 3 SMSC LAN9311/LAN9311i Table 9.11 TX Command 'B' Format DESCRIPTION Table 9.12, " ...

Page 128

... Late Collision. When set, indicates that the packet transmission was aborted after the collision window of 64 bytes. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 121. DESCRIPTION 128 DATASHEET Datasheet Section 9.7.2, Transmit Configuration Register SMSC LAN9311/LAN9311i ...

Page 129

... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN9311/LAN9311i DESCRIPTION 129 DATASHEET Revision 1.7 (06-29-10) ...

Page 130

... Data Start Offset 17-Byte Payload Data 5-Byte End Padding Figure 9.5 TX Example 1 130 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes between buffers are not transmitted SMSC LAN9311/LAN9311i ...

Page 131

... TX Command 'A' Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 6-Byte Data Start Offset Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9311/LAN9311i Memory Mapped 0 TX Command 'A' TX Command 'B' 183-Byte Payload Data 3B End Padding Figure 9.6 TX Example 2 131 DATASHEET ...

Page 132

... TX_ON bit. If the there are frames pending in the TX Data FIFO (i.e., TX Data FIFO was not purged), the transmission will resume with this data. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Transmit Configuration Register Interrupt Status Register 132 DATASHEET Datasheet (INT_STS). SMSC LAN9311/LAN9311i ...

Page 133

... RX Data FIFO. A typical host receive routine using interrupts can be seen in routine using polling can be seen in SMSC LAN9311/LAN9311i (RX_FIFO_INF). The host may read any number of controls the number of bytes that the beginning of the RX Figure 9 ...

Page 134

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface init Idle RX Interrupt Read RX Status DWORD Not Last Packet Read RX Packet init Read RX_FIFO_INF Valid Status DWORD Read RX Status DWORD Not Last Packet Read RX Packet 134 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 135

... RX Data FIFO. RX data packets are formatted in a specific manner before the host can read them as shown in status word from the RX Status FIFO, to ascertain the data size and any error conditions. SMSC LAN9311/LAN9311i Receive Datapath Control Register (RX_CFG). The RX_DUMP bit is cleared when the dump is complete. For more Section 9.9.4, " ...

Page 136

... Runt frame late collision was detected or when the Watchdog Time-out occurs. 0 Reserved. These bits are reserved. Reads 0 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION is set. 136 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...

Page 137

... RX Error (RXE) will be asserted under the following conditions: A host underrun of RX Data FIFO A host underrun of the RX Status FIFO An overrun of the RX Status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9311/LAN9311i Host MAC Control Register Interrupt Status Register (INT_STS) 137 DATASHEET (HMAC_CR) ...

Page 138

... DATASHEET Datasheet 2 C/Microwire 2 C-Bus Specification . Table 10.1. EE_SCL/EECLK PIN EE_SCL Input enabled 2 ( master and used for straps) Open-drain output 2 (from I C master) EECLK Input enabled (used for straps) Output enabled (from Microwire master) 2 C/Microwire EEPROM SMSC LAN9311/LAN9311i ...

Page 139

... If an operation is attempted and the EEPROM device does not respond within 30mS, the LAN9311/LAN9311i will time-out, and the EPC_TIMEOUT bit of the (E2P_CMD) will be set. SMSC LAN9311/LAN9311i (E2P_DATA). Section 10.2.4, "EEPROM Section 14.2.4.1, "EEPROM Command 198. Details specific to each EEPROM controller mode (I Section 10.2.2, " ...

Page 140

... E2P_CMD Register EEPROM Command Register (E2P_CMD) (E2P_CMD). Within each size range, the largest EEPROM uses all the 140 DATASHEET Datasheet EEPROM Read Idle Write E2P_CMD Register Read E2P_CMD Register EPC_BUSY = 0 Read E2P_DATA Register 2 C EEPROMs EEPROMs are supported. The SMSC LAN9311/LAN9311i is ...

Page 141

... Typically the receiver acknowledges each byte. If the master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to not drive the next byte of data so that the master may generate a stop or repeated start condition. SMSC LAN9311/LAN9311i 2 C operation are shown in ...

Page 142

... C EEPROM addressing bit order for single and double byte addressing. Control Byte Chip / Block R/~W Select Bits Double Byte Addressing 2 Figure 10 EEPROM Addressing 142 DATASHEET Datasheet data data can stable change P Data Valid Stop Condition or Ack EEPROM Command Address High Address Low Byte Byte SMSC LAN9311/LAN9311i ...

Page 143

... Chip / Block R/~W Select Bits Control Byte Chip / Block R/~W Select Bits Figure 10.5 I SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD EEPROM byte read for single and double byte addressing. Control Byte Chip / Block Select Bits 2 Figure 10 EEPROM Byte Read EEPROM Command Register (E2P_CMD) ...

Page 144

... Chip / Block Select Bits Select Bits 2 Figure 10 EEPROM Byte Write 144 DATASHEET Datasheet Section 10.2.4, "EEPROM Loader" Section 10.2.1, "EEPROM Controller EEPROM 2 C master Conclude Poll Cycle Control Byte ... R/~W Chip / Block R/~W Select Bits Section 10.2.1, "EEPROM Controller SMSC LAN9311/LAN9311i for 2 C ...

Page 145

... Table 10.5 Microwire Command Set for 9 Address Bits START INST BIT OPCODE ERASE 1 11 ERAL 1 00 SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD). Within each size range, the EEPROM SIZE 7 128 256 x 8 and 512 1024 x 8 and 2048 x 8 RESERVED for detailed Microwire timing information. ...

Page 146

... EEPROM Command Register Figure 10.7 EEPROM ERASE Cycle 146 DATASHEET Datasheet DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - Hi Hi (RDY/~BSY (RDY/~BSY) 20 DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY Hi Hi (RDY/~BSY (RDY/~BSY) 22 (E2P_CMD). The EPC_TIMEOUT SMSC LAN9311/LAN9311i ...

Page 147

... EEDI 10.2.3.4 EWDS (Erase/Write Disable) After this command is issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations, the EWEN command must be issued. EECS EECLK EEDO 1 EEDI SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD Figure 10.8 EEPROM ERAL Cycle Figure 10.9 EEPROM EWDS Cycle ...

Page 148

... EEDI Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Figure 10.10 EEPROM EWEN Cycle (E2P_CMD). The result of the read is available in the Figure 10.11 EEPROM READ Cycle 148 DATASHEET Datasheet EEPROM Data D7 D0 SMSC LAN9311/LAN9311i ...

Page 149

... EPC_TIMEOUT bit of the respond within 30mS. EECS EECLK EEDO EEDI SMSC LAN9311/LAN9311i to be written to the EEPROM location pointed to by the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the is set if the EEPROM does not respond within 30mS Figure 10.12 EEPROM WRITE Cycle to be written to every EEPROM memory location ...

Page 150

... Byte on the Network th 5 Byte on the Network th 6 Byte on the Network A5h See Table 10.8 A5h See Section 10.2.4.5, "Register Data" See Section 10.2.4.5, "Register Data" Reset Control EEPROM Command will be set. Hardware Configuration Register is cleared and no writes to the SMSC LAN9311/LAN9311i ...

Page 151

... Update LED_CFG, MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_mii registers Read Byte 12 Byte 12 = A5h Perform register data load loop Figure 10.14 EEPROM Loader Flow Diagram SMSC LAN9311/LAN9311i N Load PHY registers with current straps Y Load PHY registers with N current straps Y Write Bytes 1-6 into Host ...

Page 152

... Host MAC Address Low Register EEPROM Command Register 10.2.4.4.1). Refer to Section 4.2. speed_ duplex_ autoneg_ strap_1 strap_1 strap_1 speed_ duplex_ autoneg_ strap_2 strap_2 strap_2 speed_ duplex_pol_ SQE_test_ strap_mii strap_mii disable_strap _mii Port x PHY Auto- Port x PHY Special Modes Register SMSC LAN9311/LAN9311i are ...

Page 153

... The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte is the total number of bursts. Following this is a series of bursts, each consisting of a starting address, count, and the count x 4 bytes of data. This results in the following formula for formatting register data: SMSC LAN9311/LAN9311i Section 14.4.2.5, "Port x PHY Auto-Negotiation Advertisement Register 295. ...

Page 154

... MII Busy bit of the are cleared before performing any register write. EEPROM Command Register will be cleared. Section 15.5.2, "Reset and Configuration Strap Timing," on and Section 10.2.4.4.2, respectively. 154 DATASHEET Datasheet Switch Fabric CSR Interface Command PHY Management Interface Access (E2P_CMD). The SMSC LAN9311/LAN9311i ...

Page 155

... A boundary clock may contain multiple ports, but a maximum of one slave port is permitted. For more information on the IEEE 1588 protocol, refer to the National Institute of Standards and Technology IEEE 1588 website: http://ieee1588.nist.gov/ SMSC LAN9311/LAN9311i describes the various IEEE 1588 related blocks and how they 202. 155 DATASHEET Revision 1 ...

Page 156

... IRQ Flags Clock Capture GPIO9 IRQ Enables IRQ Flag host Figure 11.1 IEEE 1588 Block Diagram 156 DATASHEET Datasheet Figure 11.1, and consists of the To Host MAC IEEE 1588 Clock 32 Bit Addend + carry 32 Bit Accumulator inc host 64 Bit Clock To INT_STS register X9 SMSC LAN9311/LAN9311i ...

Page 157

... Preamble Octet Figure 11.2 IEEE 1588 Message Time Stamp Point SMSC LAN9311/LAN9311i summarizes the message type detection under slave and master IEEE RECEIVE Sync Delay_Req Figure 11.2, the message time stamp point is defined as the Message Timestamp Point Ethernet Start of Frame ...

Page 158

... Section 11.6, "IEEE 1588 Interrupts," on page 161 1588 Interrupt Status and Enable Register 158 DATASHEET Datasheet for details on these modes. DELAY (+/- 10 nS 120 nS Port x 1588 Source UUID Low- and Port x 1588 Source UUID for information (1588_INT_STS_EN). 1588 Configuration Register is set. Refer to Section for additional information on SMSC LAN9311/LAN9311i ...

Page 159

... Note: For proper routing of the PTP packets, the host must program an entry into the switch engine Address Logic Resolution (ALR) Table. The MAC address should be one of the reserved Multicast addresses in bits must also be set. Refer to SMSC LAN9311/LAN9311i which enables/disables the corresponding address (1588_AUX_MAC_LO). The user defined address may be (1588_CONFIG). A summary of the supported PTP multicast addresses and Table 11 ...

Page 160

... Accumulator every 100 MHz clock. Upon overflow 100 MHz 100 MHz Table 11.4. These values should be adjusted based on the 1588_CLOCK_ADDEND (Addend) 547AE147h 80000000h A8F5C28Fh C0000000h E6666666h 160 DATASHEET Datasheet 1588 Clock High-DWORD Register register is written with ADJUSTMENT PRECISION % -8 7.1*10 -8 4.7*10 -8 3.5*10 -8 3.1*10 -8 2.6*10 SMSC LAN9311/LAN9311i ...

Page 161

... GPIO inputs must be active for greater than recognized as clear events. For more information on IEEE 1588 GPIO interrupts, refer to page 164. Refer to Chapter 5, "System Interrupts," on page 49 LAN9311/LAN9311i interrupts. SMSC LAN9311/LAN9311i 1588 Clock Target High-DWORD Register 1588 Interrupt Status and Enable Register 1588 Configuration Register (1588_CONFIG) (1588_CLOCK_TARGET_RELOAD_LO)) ...

Page 162

... IRQ interrupt (if GPT_INT_EN (INT_STS)), and continues counting. GPT_INT is a sticky bit. for additional information on the GPT interrupt. Free Running 25MHz Counter Register 162 DATASHEET Datasheet with the value in the when the is asserted (1 Section 5.2.7, "General (FREE_RUN). On SMSC LAN9311/LAN9311i ...

Page 163

... Note: For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the Purpose I/O Data & Direction Register (GPIO_DATA_DIR) the General Purpose I/O Configuration Register SMSC LAN9311/LAN9311i 193. General Purpose I/O Data & Direction Register (GPIO_CFG)) Section 13.3, "LED Operation" ...

Page 164

... DATASHEET Datasheet for additional information and 1588 Interrupt Status and (GPIO_CFG). These bits 1588 Clock Target High-DWORD Register 1588 Clock High- (1588_CLOCK_LO). 1588 Interrupt Status and Enable Register (GPIO_CFG). (GPIO_INT_STS_EN). Reading the bit 12 (GPIO). For more SMSC LAN9311/LAN9311i 1588 1588 49. ...

Page 165

... Port 0 nP1LED2 Link / Activity (GPIO2) Port 1 SMSC LAN9311/LAN9311i General Purpose I/O Interrupt Status and Enable 1588 Interrupt Status and Enable Register 1588 Interrupt Status and Enable Register (LED_CFG). These bits allow the configuration of each LED pin to indicate LED Configuration Register (LED_CFG) ...

Page 166

... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface LED_CFG[9:8] (LED_FUN[1:0]) Full-duplex / Collision Full-duplex / Collision Port 1 Port 1 10Link / Activity Speed Port 1 Port 1 Table 13.1 are described below: 166 DATASHEET Datasheet TXEN Port 1 RXDV Port 1 SMSC LAN9311/LAN9311i ...

Page 167

... Note: Not all LAN9311/LAN9311i registers are memory mapped or directly addressable. For details on the accessibility of the various LAN9311/LAN9311i registers, refer the register sub-sections listed above. Figure 14.1 LAN9311/LAN9311i Base Register Memory Map SMSC LAN9311/LAN9311i Section 1.3, "Register Nomenclature," on page 3FFh RESERVED ...

Page 168

... Section 8.4, "Host Endianess". Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (HW_CFG). Refer to Section 9.7.3, "FIFO Memory Allocation for additional information on FIFO size configuration. Section 14.2.2, "Host MAC & 168 DATASHEET Datasheet FIFO’s". SMSC LAN9311/LAN9311i ...

Page 169

... PMT_CTRL 088h RESERVED 08Ch GPT_CFG 090h GPT_CNT 094h - 098h RESERVED SMSC LAN9311/LAN9311i REGISTER NAME Chip ID and Revision Register, Interrupt Configuration Register, Interrupt Status Register, Interrupt Enable Register, Reserved for Future Use Byte Order Test Register, FIFO Level Interrupts Register, Receive Configuration Register, ...

Page 170

... Port 2 1588 Clock High-DWORD Transmit Capture Register, Section 14.2.5.5 Port 2 1588 Clock Low-DWORD Transmit Capture Register, Section 14.2.5.6 Port 2 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register, 170 DATASHEET Datasheet Section 14.2.9.7 Section 14.2.2.8 Section 14.2.5.3 Section 14.2.5.7 Section 14.2.5.3 Section 14.2.5.7 SMSC LAN9311/LAN9311i ...

Page 171

... SMSC LAN9311/LAN9311i REGISTER NAME Port 2 1588 Source UUID Low-DWORD Transmit Capture Register, Section 14.2.5.8 Port 0 1588 Clock High-DWORD Receive Capture Register, Section 14.2.5.1 Port 0 1588 Clock Low-DWORD Receive Capture Register, Section 14.2.5.2 ...

Page 172

... Switch Engine CSR Interface Direct Data Register, Section 14.2.6.8 Reserved for Future Use 172 DATASHEET Datasheet Section 14.2.6.1 Section 14.2.6.2 Section 14.2.6.3 Section 14.2.4.1 Section 14.2.4.2 Section 14.2.3.4 Section 14.2.8.1 Section 14.2.8.2 Section 14.2.8.3 Section 14.2.8.4 Section 14.2.6.6 Section 14.2.6.7 SMSC LAN9311/LAN9311i ...

Page 173

... This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently de-asserted. This bit has no effect on any internal interrupt status bits. 0: Disable output on IRQ pin 1: Enable output on IRQ pin 7:5 RESERVED SMSC LAN9311/LAN9311i Chapter 5, "System Interrupts," on page 054h Size: DESCRIPTION 173 DATASHEET 49 ...

Page 174

... Configuration Register (HW_CFG) Register (RESET_CTL) Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION register or the DIGITAL_RST bit in the is set. 174 DATASHEET Datasheet TYPE DEFAULT R/W 0b NASR Note 14 R/W 0b NASR Note 14.1 Hardware Reset Control SMSC LAN9311/LAN9311i ...

Page 175

... RX DMA Interrupt (RXD_INT) This interrupt is issued when the amount of data programmed in the RX DMA Count (RX_DMA_CNT) field of the (RX_CFG) has been transferred out of the RX Data FIFO. SMSC LAN9311/LAN9311i 058h Size: Interrupt Enable Register DESCRIPTION Interrupt Enable 1588 Interrupt Status and Enable ...

Page 176

... Section 9.8.7, "Transmitter Errors," on page 132 General Purpose TX Data Available Level (FIFO_INT). TX Status Level field of the FIFO Level Interrupt 176 DATASHEET Datasheet TYPE DEFAULT R/ R/WC 0b must first be R/WC 0b R/WC 0b R/ R/WC 0b R/WC 0b field of R/WC 0b R/ SMSC LAN9311/LAN9311i ...

Page 177

... This interrupt is generated when the RX Status FIFO is full Status FIFO Level Interrupt (RSFL) This interrupt is generated when the RX Status FIFO reaches the programmed level in the Register (FIFO_INT). 2:0 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION RX Status Level field of the FIFO Level Interrupt 177 DATASHEET TYPE DEFAULT ...

Page 178

... DESCRIPTION 178 DATASHEET Datasheet 32 bits register TYPE DEFAULT R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R R/W 0b R R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b SMSC LAN9311/LAN9311i ...

Page 179

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 5 RESERVED - This bit must be written with 0b for proper operation Status FIFO Full Interrupt Enable (RSFF_EN Status FIFO Level Interrupt Enable (RSFL_EN) 2:0 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION 179 DATASHEET TYPE DEFAULT R/W 0b R/W 0b R/W ...

Page 180

... Interrupt Status Register will be generated. When the TX TX Status FIFO Level Interrupt Status Register will be generated. When the RX RX Status FIFO Level Interrupt Status Register 180 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 48h R/W 00h R/W 00h R/W 00h SMSC LAN9311/LAN9311i ...

Page 181

... RX data and status pointers are cleared to zero. Note: Please refer to Dump)," on page 135 of RX_DUMP. SMSC LAN9311/LAN9311i Host MAC CSR Interface Command Register Host MAC CSR Interface Data Register Section 14.3, "Host MAC Control and Status 271. For more information on the Host MAC, refer to 113 ...

Page 182

... Modifications to the upper bits will take affect on the next DWORD read. 7:0 RESERVED Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 182 DATASHEET Datasheet TYPE DEFAULT RO - R/W 00000b RO - SMSC LAN9311/LAN9311i ...

Page 183

... When this bit is set, the Host MAC transmitter will finish the current frame, and will then stop transmitting. When the transmitter has stopped this bit will clear. All writes to this bit are ignored while this bit is high. SMSC LAN9311/LAN9311i 070h Size: ...

Page 184

... Forward," on page 135 of RX_FFWD. 30:0 RESERVED Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 078h Size: DESCRIPTION Section 9.9.1.1, "Receive Data FIFO Fast for detailed information regarding the use 184 DATASHEET Datasheet 32 bits TYPE DEFAULT R SMSC LAN9311/LAN9311i ...

Page 185

... This field indicates the amount of space, in bytes, used in the RX Data FIFO. For each receive frame, the field is incremented by the length of the receive data. In cases where the payload does not end on a DWORD boundary, the total will be rounded up to the nearest DWORD. SMSC LAN9311/LAN9311i 07Ch Size: DESCRIPTION ...

Page 186

... This field indicates the amount of space, in bytes, available in the TX Data FIFO. The application should never write more than is available, as indicated by this value. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 080h Size: DESCRIPTION 186 DATASHEET Datasheet 32 bits TYPE DEFAULT 1200h SMSC LAN9311/LAN9311i ...

Page 187

... This counter is incremented every time a receive frame is dropped by the Host MAC. RX_DFC is cleared on any read of this register. Note: The interrupt RXDFH_INT (bit 23 of the (INT_STS)) can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9311/LAN9311i 0A0h Size: DESCRIPTION Interrupt Status Register 187 ...

Page 188

... Size: Host MAC CSR Interface Data Register (MAC_CSR_DATA) Section 14.3, "Host MAC Control and Status 271. For more information on the Host MAC, refer to 113. DESCRIPTION (MAC_CSR_DATA). 188 DATASHEET Datasheet 32 bits Chapter 9, "Host TYPE DEFAULT R R R/W 00h 271. SMSC LAN9311/LAN9311i to ...

Page 189

... Note: The MAC_CSR_CMD and MAC_CSR_DATA registers must not be modified until the CSR Busy bit is cleared in the MAC_CSR_CMD register. SMSC LAN9311/LAN9311i 0A8h Size: Host MAC CSR Interface Command Register Section 14.3, "Host MAC Control and Status 271. For more information on the Host MAC, refer to 113 ...

Page 190

... DESCRIPTION Host MAC Flow Control Register Port 0(Host MAC) Manual Flow Control Port 0(Host MAC) Manual Flow Control Table 14.2, describing Backpressure Duration bit 190 DATASHEET Datasheet 32 bits in the Host MAC CSR TYPE DEFAULT RO - R/W 00h R/W 00h R/W 0h SMSC LAN9311/LAN9311i ...

Page 191

... Data FIFO level is reached. The MAC will queue the pause frame transmission for the next available window. Setting this bit overrides bits [3:1] of this register. Table 14.2 Backpressure Duration Bit Mapping [7: SMSC LAN9311/LAN9311i DESCRIPTION BACKPRESSURE DURATION 100Mbs Mode 5uS 10uS 15uS 25uS 50uS 100uS 150uS 200uS 250uS 191 ...

Page 192

... Table 14.2 Backpressure Duration Bit Mapping (continued Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface BACKPRESSURE DURATION 300uS 350uS 400uS 450uS 500uS 550uS 600uS 192 DATASHEET Datasheet 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS 602.2uS SMSC LAN9311/LAN9311i ...

Page 193

... GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8) This bit determines if the 1588 clock event output on GPIO 8 is active high or low. 0: 1588 clock event output active low 1: 1588 clock event output active high SMSC LAN9311/LAN9311i 1E0h Size: DESCRIPTION 1588 Interrupt Status and Enable Register General (GPIO_INT_STS_EN) ...

Page 194

... GPIOx Clock Event Polarity Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 1588 Clock Event Pin State no not driven yes driven low no driven low yes not driven 194 DATASHEET Datasheet TYPE DEFAULT R/W 0h SMSC LAN9311/LAN9311i ...

Page 195

... For GPIOs 11-10 and 7-0, the pin direction is determined by the GPDIR bits of this register. For GPIOs 9 and 8, the pin direction is determined by the GPDIR bits and the 1588_GPIO_OE bits in the Configuration Register (GPIO_CFG). SMSC LAN9311/LAN9311i 1E4h Size: DESCRIPTION General Purpose I/O 195 ...

Page 196

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1E8h Size: Interrupt Status Register Interrupt Enable Register (INT_EN) Chapter 5, "System Interrupts," on page 49 DESCRIPTION in order to cause the General Purpose I/O Configuration 196 DATASHEET Datasheet 32 bits (INT_STS). Writing a 1 must also be set in order TYPE DEFAULT R/WC 0h SMSC LAN9311/LAN9311i for ...

Page 197

... Note 14.3 The default value of this field is determined by the configuration strap LED_en_strap[7:0]. Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 40 SMSC LAN9311/LAN9311i 1BCh Size: DESCRIPTION 165 ...

Page 198

... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1B4h Size: DESCRIPTION (E2P_DATA). The E2P_CMD and EEPROM Controller Timeout Hardware Configuration Register (HW_CFG). After Section 10.2.4, "EEPROM Loader," on 198 DATASHEET Datasheet Section 10.2, for additional information on the various 32 bits TYPE DEFAULT R SMSC LAN9311/LAN9311i ...

Page 199

... RELOAD operation will fail. The CFG_LOADED bit indicates a successful load. Following this command, the device will enter the not ready state. The READY bit in the Hardware Configuration Register (HW_CFG) to determine then the RELOAD is complete. 27:19 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION [28] Operation 0 READ 1 ...

Page 200

... This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 200 DATASHEET Datasheet TYPE DEFAULT RO 0b R/WC 0b R/WC 0b R/W 0000h SMSC LAN9311/LAN9311i ...

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