EVB9311 SMSC, EVB9311 Datasheet - Page 323

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.5.1.4
BITS
31:7
4:3
6
5
2
1
0
RESERVED
Buffer Manager Interrupt (BM)
Set when any unmasked bit in the
Register (BM_IPR)
Switch Engine Interrupt (SWE)
Set when any unmasked bit in the
(SWE_IPR)
RESERVED
Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see
14.5.2.44, on page
Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see
14.5.2.44, on page
Port 0 MAC Interrupt (MAC_MII)
Set when any unmasked bit in the MAC_IPR_MII register (see
14.5.2.44, on page
Switch Global Interrupt Pending Register (SW_IPR)
This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates
an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related
interrupts in this register may be masked via the
register. When an unmasked switch fabric interrupt is generated in this register, the interrupt will trigger
the SWITCH_INT bit in the
Interrupts," on page 49
Register #:
is triggered. This bit is cleared upon a read.
367) is triggered. This bit is cleared upon a read.
367) is triggered. This bit is cleared upon a read.
367) is triggered. This bit is cleared upon a read.
is triggered. This bit is cleared upon a read.
for more information.
0005h
DESCRIPTION
Interrupt Status Register
Switch Engine Interrupt Pending Register
Buffer Manager Interrupt Pending
DATASHEET
323
Size:
Switch Global Interrupt Mask Register (SW_IMR)
(INT_STS). Refer to
Section
Section
Section
32 bits
TYPE
RO
RC
RC
RO
RC
RC
RC
Chapter 5, "System
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
-
-