EVB9311 SMSC, EVB9311 Datasheet - Page 181

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.2
14.2.2.1
31:30
29:28
27:16
BITS
15
RX End Alignment (RX_EA)
This field specifies the alignment that must be maintained on the last data
transfer of a buffer. The LAN9311/LAN9311i will add extra DWORD’s of
data up to the alignment specified in the table below. The host is
responsible for removing these extra DWORD’s. This mechanism can be
used to maintain cache line alignment on host processors.
Note:
RESERVED
RX DMA Count (RX_DMA_CNT)
This 12-bit field indicates the amount of data, in DWORD’s, to be
transferred out of the RX Data FIFO before asserting the
(RXD_INT). After being set, this field is decremented for each DWORD of
data that is read from the RX Data FIFO. This field can be overwritten with
a new value before it reaches zero.
Force RX Discard (RX_DUMP)
When a 1 is written to this bit, the RX Data and Status FIFO’s are cleared
of all pending data and the RX data and status pointers are cleared to zero.
Note:
Host MAC & FIFO’s
This section details the Host MAC and TX/RX FIFO related System CSR’s.
These Host Bus Interface accessible registers allow for the configuration of the TX/RX FIFO’s, Host
MAC and indirect access to the complete set of Host MAC CSR’s. The Host MAC CSR’s are
accessible through the Host Bus Interface via the
(MAC_CSR_CMD)
Note: For more information on the TX/RX FIFO’s, refer to
Note: The full list of Host MAC CSR’s are described in
Receive Configuration Register (RX_CFG)
This register controls the Host MAC receive engine.
VALUES
[31:30]
BIT
00
01
10
11
The desired RX End Alignment must be set before reading a
packet. The RX End Alignment can be changed between reading
receive packets, but must not be changed if the packet is partially
read.
Please refer to
Dump)," on page 135
of RX_DUMP.
Registers," on page
MAC," on page
Offset:
4-Byte Alignment
16-Byte Alignment
32-Byte Alignment
RESERVED
and
Section 9.9.1.2, "Force Receiver Discard (Receiver
113.
Host MAC CSR Interface Data Register
06Ch
DESCRIPTION
271. For more information on the Host MAC, refer to
for a detailed description regarding the use
END ALIGNMENT
DATASHEET
181
Size:
Host MAC CSR Interface Command Register
RX DMA Interrupt
Section 14.3, "Host MAC Control and Status
Section 14.1, "TX/RX FIFO
32 bits
(MAC_CSR_DATA).
TYPE
R/W
R/W
WO
RO
SC
Revision 1.7 (06-29-10)
Chapter 9, "Host
Ports".
DEFAULT
000h
00b
0b
-