EVB9311 SMSC, EVB9311 Datasheet - Page 191

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
BITS
3
2
1
0
Flow Control on Multicast Frame (FCMULT)
When this bit is set, the Host MAC will assert back pressure when the AFC
level is reached and a multicast frame is received. This field has no function
in full-duplex mode.
0: Flow Control on Multicast Frame Disabled
1: Flow Control on Multicast Frame Enabled
Flow Control on Broadcast Frame (FCBRD)
When this bit is set, the Host MAC will assert back pressure when the AFC
level is reached and a broadcast frame is received. This field has no function
in full-duplex mode.
0: Flow Control on Broadcast Frame Disabled
1: Flow Control on Broadcast Frame Enabled
Flow Control on Address Decode (FCADD)
When this bit is set, the Host MAC will assert back pressure when the AFC
level is reached and a frame addressed to the Host MAC is received. This
field has no function in full-duplex mode.
0: Flow Control on Address Decode Disabled
1: Flow Control on Address Decode Enabled
Flow Control on Any Frame (FCANY)
When this bit is set, the Host MAC will assert back pressure, or transmit a
pause frame when the AFC level is reached and any frame is received.
Setting this bit enables full-duplex flow control when the Host MAC is
operating in full-duplex mode.
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the Host MAC address and will send a JAM upon receipt
of a valid preamble (i.e., immediately at the beginning of the next frame after
the RX Data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the Host MAC to send a pause frame when the RX
Data FIFO level is reached. The MAC will queue the pause frame
transmission for the next available window.
Setting this bit overrides bits [3:1] of this register.
[7:4]
0h
1h
2h
3h
4h
5h
6h
7h
8h
Table 14.2 Backpressure Duration Bit Mapping
DESCRIPTION
100Mbs Mode
DATASHEET
100uS
150uS
200uS
250uS
10uS
15uS
25uS
50uS
5uS
191
BACKPRESSURE DURATION
10Mbs Mode
102.2uS
152.2uS
202.2uS
252.2uS
12.2uS
17.2uS
27.2uS
52.2uS
TYPE
7.2uS
R/W
R/W
R/W
R/W
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b