EVB9311 SMSC, EVB9311 Datasheet - Page 49

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 5 System Interrupts
SMSC LAN9311/LAN9311i
5.1
5.2
This chapter describes the system interrupt structure of the LAN9311/LAN9311i. The
LAN9311/LAN9311i provides a multi-tier programmable interrupt structure which is controlled by the
System Interrupt Controller. The programmable system interrupts are generated internally by the
various LAN9311/LAN9311i sub-modules and can be configured to generate a single external host
interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the
user with the ability to optimize performance dependent upon the application requirements. The IRQ
interrupt buffer type, polarity, and de-assertion interval are modifiable. The IRQ interrupt can be
configured as an open-drain output to facilitate the sharing of interrupts with other devices. All internal
interrupts are maskable and capable of triggering the IRQ interrupt.
The LAN9311/LAN9311i is capable of generating the following interrupt types:
All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure,
as shown in
Status Register
(IRQ_CFG).
The
enable/disable all interrupts from the various LAN9311/LAN9311i sub-modules, combining them
together to create the IRQ interrupt. These registers provide direct interrupt access/configuration to the
Host MAC, General Purpose Timer, software, and device ready interrupts. These interrupts can be
monitored, enabled/disabled, and cleared, directly within these two registers. In addition, interrupt
event indications are provided for the 1588 Time Stamp, Switch Fabric, Port 1 & 2 Ethernet PHYs,
Power Management, and GPIO interrupts. These interrupts differ in that the interrupt sources are
generated and cleared in other sub-block registers. The INT_STS register does not provide details on
what specific event within the sub-module caused the interrupt, and requires the software to poll an
additional sub-module interrupt register (as shown in
source and clear it. For interrupts which involve multiple registers, only after the interrupt has been
serviced and cleared at its source will it be cleared in the INT_STS register.
The
output pin as well as configuring its properties. The IRQ_CFG register allows the modification of the
IRQ pin buffer type, polarity, and de-assertion interval. The de-assertion timer guarantees a minimum
interrupt de-assertion period for the IRQ output and is programmable via the INT_DEAS field of the
Interrupt Configuration Register
de-assertion interval starts when the IRQ pin de-asserts, regardless of the reason.
Note: The de-assertion timer does not apply to the PME interrupt. Assertion of the PME interrupt
Functional Overview
Interrupt Sources
1588 Time Stamp Interrupts
Switch Fabric Interrupts
Ethernet PHY Interrupts
GPIO Interrupts
Host MAC Interrupts
Power Management Interrupts
General Purpose Timer Interrupt
Software Interrupt
Device Ready Interrupt
Interrupt Configuration Register (IRQ_CFG)
Interrupt Status Register (INT_STS)
does not affect the de-assertion timer.
Figure
(INT_STS),
5.1. At the top level of the LAN9311/LAN9311i interrupt structure are the
(GPIO[11:0])
(General Purpose)
(FIFOs)
(Buffer Manager, Switch Engine, and Port 2,1,0 MACs)
(Port 1,2 PHYs)
Interrupt Enable Register
(IRQ_CFG). A setting of all zeros disables the de-assertion timer. The
(Port 2,1,0 and GPIO 9,8)
DATASHEET
(GPT)
49
and
Interrupt Enable Register (INT_EN)
is responsible for enabling/disabling the IRQ interrupt
(INT_EN), and
Figure
5.1) to determine the exact interrupt
Interrupt Configuration Register
Revision 1.7 (06-29-10)
aggregate and
Interrupt