EVB9311 SMSC, EVB9311 Datasheet - Page 368

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Revision 1.7 (06-29-10)
14.5.3
14.5.3.1
BITS
31:3
2
1
0
RESERVED
Make Entry
When set, the contents of ALR_WR_DAT_0 and ALR_WR_DAT_1 are
written into the ALR table. The ALR logic determines the location where the
entry is written. This command can also be used to change or delete a
previously written or automatically learned entry. This bit has no affect when
written low. This bit must be cleared once the ALR Make command is
completed, which can be determined by the ALR Status bit in the
Engine ALR Command Status Register (SWE_ALR_CMD_STS)
Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table
and the ALR table is searched for the first valid entry, which is loaded into
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. The bit has no affect
when written low. This bit must be cleared after it is set.
Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. This bit has no affect
when written low. This bit must be cleared after it is set.
Switch Engine CSRs
This section details the switch engine related CSRs. These registers allow configuration and monitoring
of the various switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables.
A list of the general switch CSRs and their corresponding register numbers is included in
Switch Engine ALR Command Register (SWE_ALR_CMD)
This register is used to manually read and write MAC addresses from/into the ALR table.
For a read access, the
Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
1(Get First Entry) or bit 0(Get Next Entry) of this register.
For write access, the
Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
MAC address, followed by the setting of bit 2(Make Entry) of this register. The Make Pending bit in the
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
command is finished.
Refer to
Register #:
Chapter 6, "Switch Fabric," on page 55
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
1800h
DESCRIPTION
DATASHEET
368
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
for more information.
should be read following the setting of bit
registers should first be written with the
register.
32 bits
Switch
register indicates when the
TYPE
R/W
R/W
R/W
SMSC LAN9311/LAN9311i
RO
DEFAULT
Table
and
and
Datasheet
0b
0b
0b
-
Switch
Switch
14.12.