EVB9311 SMSC, EVB9311 Datasheet - Page 110

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Revision 1.7 (06-29-10)
8.5.7
D[15:0] (OUTPUT)
FIFO_SEL
END_SEL
nCS, nRD
A[x:3]
A[2:1]
RX Data FIFO Direct PIO Burst Reads
In this mode only A[2:1] are decoded, and any burst read of the LAN9311/LAN9311i will read the RX
Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful
when the host processor must increment its address when accessing the LAN9311/LAN9311i. Timing
is identical to a PIO burst read, and the FIFO_SEL and END_SEL signals have the same timing
characteristics as the address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORD read
cycles. RX Data FIFO direct PIO burst reads can be performed using chip select (nCS) or read enable
(nRD). An RX Data FIFO direct PIO burst read begins when both nCS and nRD are asserted. Either
or both of these control signals must de-assert between bursts for the period specified in
“RX Data FIFO Direct PIO Burst Read Cycle Timing Values,” on page
either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Read data is valid as indicated in the functional timing diagram in
Note: A[1] must toggle during burst reads. Fresh data is supplied each time A[1] is toggled.
Please refer to
the AC timing specifications for PIO RX Data FIFO direct PIO burst read operations.
Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation
Section 15.5.7, "RX Data FIFO Direct PIO Burst Read Cycle Timing," on page 450
(READ DATA FROM RX DATA FIFO)
DATASHEET
110
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Figure
450. The burst cycle ends when
8.6.
SMSC LAN9311/LAN9311i
Table 15.11,
Datasheet
for