EVB9311 SMSC, EVB9311 Datasheet - Page 289

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.4.2.1
BITS
15
14
13
12
11
10
Reset (PHY_RST)
When set, this bit resets all the Port x PHY registers to their default state,
except those marked as NASR type. This bit is self clearing.
0: Normal operation
1: Reset
Loopback (PHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the switch fabric are not sent to network. Instead, they are looped back
into the switch fabric.
Note:
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
Speed Select LSB (PHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Port x PHY when the
Negotiation (PHY_AN)
0: 10 Mbps
1: 100 Mbps
Auto-Negotiation (PHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the
LSB (PHY_SPEED_SEL_LSB)
overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
Power Down (PHY_PWR_DWN)
This bit controls the power down mode of the Port x PHY. After this bit is
cleared the PHY may auto-negotiate with it’s partner station. This process
can take up to a few seconds to complete. Once Auto-Negotiation is
complete, bit 5
Register (PHY_BASIC_STATUS_x)
Note:
0: Normal operation
1: General power down mode
RESERVED
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
This read/write register is used to configure the Port x PHY.
Note: This register is re-written in its entirety by the EEPROM Loader following the release of reset
If loopback is enabled during half-duplex operation, then the
Enable Receive Own Transmit bit in the
Configuration Register (MAC_RX_CFG_x)
specified port. Otherwise, the switch fabric will ignore receive
activity when transmitting in half-duplex mode.
The PHY_AN bit of this register must be cleared before setting this
bit.
or a RELOAD command. Refer to
additional information.
Index (decimal): 0
(Auto-Negotiation
bit is disabled.
DESCRIPTION
and
Complete) of the
will be set.
Duplex Mode (PHY_DUPLEX)
DATASHEET
289
Section 10.2.4, "EEPROM Loader," on page 150
Port x MAC Receive
Size:
Port x PHY Basic Status
must be set for the
Speed Select
Auto-
16 bits
bits are
TYPE
R/W
R/W
R/W
R/W
R/W
RO
SC
Revision 1.7 (06-29-10)
Note 14.49
Note 14.50
DEFAULT
0b
0b
0b
-
for