EVB9311 SMSC, EVB9311 Datasheet - Page 133

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
9.9
9.9.1
When an Ethernet Packet is received, the Host MAC Interface Layer (MIL) first begins to transfer the
RX data. This data is loaded into the RX Data FIFO. The RX Data FIFO pointers are updated as data
is written into the FIFO.
The last transfer from the MIL is the RX status word. The LAN9311/LAN9311i implements a separate
FIFO for the RX status words. The total available RX data and status queued in the RX FIFO can be
read from the
available RX status words before reading the RX Data FIFO.
The host must use caution when reading the RX data and status. The host must never read more data
than what is available in the FIFO’s. If this is attempted an underrun condition will occur. If this error
occurs, the Ethernet controller will assert the Receiver Error (RXE) interrupt. If an underrun condition
occurs, a soft reset is required to regain host synchronization.
A configurable beginning offset is supported in the LAN9311/LAN9311i. The RX data Offset field in the
Receive Configuration Register (RX_CFG)
data buffer is shifted. The host can set an offset from 0-31 bytes. The offset may be changed in
between RX packets, but it must not be changed during an RX packet read.
The LAN9311/LAN9311i can be programmed to add padding at the end of a receive packet in the event
that the end of the packet does not align with the host burst boundary. This feature is necessary when
the LAN9311/LAN9311i is operating in a system that always performs multi-DWORD bursts. In such
cases the LAN9311/LAN9311i must guarantee that it can transfer data in multiples of the Burst length
regardless of the actual packet length. When configured to do so, the LAN9311/LAN9311i will add extra
data at the end of the packet to allow the host to perform the necessary number of reads so that the
Burst length is not cut short. Once a packet has been padded by the H/W, it is the responsibility of the
host to interrogate the packet length field in the RX status and determine how much padding to discard
at the end of the packet.
It is possible to read multiple packets out of the RX Data FIFO in one continuous stream. It should be
noted that the programmed Offset and Padding will be added to each individual packet in the stream,
since packet boundaries are maintained.
RX Slave PIO Operation
Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received
packet out of the RX Data FIFO. The host will remain in the idle state until it receives an indication
(interrupt or polling) that data is available in the RX Data FIFO. The host will then read the RX Status
FIFO to get the packet status, which will contain the packet length and any other status information.
The host should perform the proper number of reads, as indicated by the packet length plus the start
offset and the amount of optional padding added to the end of the frame, from the RX Data FIFO. A
typical host receive routine using interrupts can be seen in
routine using polling can be seen in
RX Data Path Operation
RX FIFO Information Register
DATASHEET
Figure
133
controls the number of bytes that the beginning of the RX
9.8.
(RX_FIFO_INF). The host may read any number of
Figure
9.7, while a typical host receive
Revision 1.7 (06-29-10)