EVB9311 SMSC, EVB9311 Datasheet - Page 107

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
8.5.4
D[15:0] (OUTPUT)
PIO Reads
PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can
be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both
nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for
the period specified in
either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Read data is valid as indicated in the functional timing diagram in
The endian select signal (END_SEL) has the same timing characteristics as the address lines.
Please refer to
for PIO read operations.
Note: Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer
END_SEL
nCS, nRD
to
Section 8.5.2
A[x:1]
Section 15.5.4, "PIO Read Cycle Timing," on page 447
Figure 8.3 Functional Timing for PIO Read Operation
Table 15.8, “PIO Read Cycle Timing Values,” on page
for information on these restrictions.
DATASHEET
107
VALID
VALID
VALID
Figure
for the AC timing specifications
8.3.
447. The cycle ends when
Revision 1.7 (06-29-10)