EVB9311 SMSC, EVB9311 Datasheet - Page 39

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
4.2.2.2
4.2.3
4.2.3.1
4.2.3.2
(64KB for I
58mS for Microwire EEPROM.
Soft Reset (SRST)
A soft reset is performed by setting the SRST bit of the
A soft reset will reset the HBI, Host MAC, and System CSRs below address 100h. The soft reset also
clears any TX or RX errors in the Host MAC transmitter and receiver (TXE/RXE). This reset does not
latch the configuration straps. On soft reset, the EEPROM Loader is run, but loads only the MAC
address into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
A soft reset typically takes 590uS, plus an additional time (550uS for I
data is loaded from the EEPROM via the EEPROM Loader.
Single-Module Resets
A single-module reset will reset only the specified module. Single-module resets do not latch the
configuration straps or initiate the EEPROM Loader. A single-module reset is initiated by assertion of
the following:
Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the PHY2_RST bit of the
(RESET_CTL)
Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared.
No other modules of the LAN9311/LAN9311i are affected by this reset.
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
information.
Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the
Register (RESET _CTL)
(PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 2 PHY, register bits designated as NASR are not
Refer to
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the PHY1_RST bit of the
(RESET_CTL)
Upon completion of the Port 1 PHY reset, the PHY1_RST and Reset bits are automatically cleared.
No other modules of the LAN9311/LAN9311i are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
information.
Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the
Register (RESET _CTL)
Port 2 PHY Reset
Port 1 PHY Reset
Virtual PHY Reset
reset.
Section 7.2.10, "PHY Resets," on page 95
2
C, 2KB for Microwire) will complete in approximately 6.0 seconds for I
or the Reset bit in the
or the Reset bit in the
until it clears. Under normal conditions, the PHY2_RST and Reset bit will
or the Reset bit in the
or the Reset bit in the
Section 7.2.9, "PHY Power-Down Modes," on page 94
Section 7.2.9, "PHY Power-Down Modes," on page 94
DATASHEET
Port x PHY Basic Control Register
Port x PHY Basic Control Register
39
for additional information on Port 2 PHY resets.
Hardware Configuration Register
Port x PHY Basic Control Register
Port x PHY Basic Control Register
2
C, 170uS for Microwire) when
(PHY_BASIC_CONTROL_x).
(PHY_BASIC_CONTROL_x).
Reset Control Register
Reset Control Register
Revision 1.7 (06-29-10)
2
C EEPROM, and
Reset Control
Reset Control
for additional
for additional
(HW_CFG).