EVB9311 SMSC, EVB9311 Datasheet - Page 265

• Manufacturer Part Number: EVB9311
• Description: EVALUATION BOARD LAN9311-NU
• Manufacturer: SMSC
• Series: 0133r

Specifications of EVB9311

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9311
• Primary Attributes: 2 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: 2 PHYs with HP Auto-MDIX, Auto- Flow Control, 32-bit CRC, MDI/MDI-X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1076

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
BITS
8:7
9
6
5
4
3
2
1
Wake-On-LAN Enable (WOL_EN)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon a WOL event. When set, the
PME_INT bit in the
upon a WOL event, regardless of the setting of the PME_EN bit.
RESERVED
PME Buffer Type (PME_TYPE)
When this bit is cleared, the PME pin functions as an open-drain buffer for
use in a wired-or configuration. When set, the PME pin is a push-pull driver.
Note:
0: PME pin open-drain output
1: PME pin push-pull driver
Wake On LAN Status (WOL_STS)
This bit indicates that a wake-up frame or magic packet was detected by the
Host MAC.
In order to clear this bit, it is required that the event in the Host MAC be
cleared as well. The event sources are described in
Management," on page
RESERVED
PME Indication (PME_IND)
The PME signal can be configured as a pulsed output or a static signal,
which is asserted upon detection of a wake-up event. When set, the PME
signal will pulse active for 50mS upon detection of a wake-up event. When
cleared, the PME signal is driven continuously upon detection of a wake-up
event.
0: PME 50mS pulse on detection of event
1: PME driven continuously on detection of event
The PME signal can be deactivated by clearing the WOL_STS bit or by
clearing the appropriate enable.
PME Polarity (PME_POL)
This bit controls the polarity of the PME signal. When set, the PME output
is an active high signal. When cleared, it is active low.
Note:
0: PME active low
1: PME active high
PME Enable (PME_EN)
When set, this bit enables the external PME signal pin. When cleared, the
external PME signal is disabled.
Note:
0: PME pin disabled
1: PME pin enabled
When PME is configured as an open-drain output, the PME_POL
field of this register is ignored and the output is always active low.
When PME is configured as an open-drain output, this field is
ignored and the output is always active low.
This bit does not affect the PME_INT interrupt bit of the
Status Register
Interrupt Status Register (INT_STS)
46.
(INT_STS).
DESCRIPTION
DATASHEET
265
Section 4.3, "Power
will also be asserted
Interrupt
NASR
NASR
R/WC
TYPE
R/W
R/W
R/W
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
-
-