LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 80

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

3-16
R
DT[1:0]
DPR
R
NC
R
PCI Functional Description
Reserved
DEVSEL/Timing
These bits encode the timing of DEVSEL/. These are
encoded as
0b00
0b01
0b10
0b11
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C875 supports a value of 0b01.
Data Parity Reported
This bit is set when the following conditions are met:
Reserved
New Capabilities
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
Reserved
The bus agent asserted PERR/ itself or observed
PERR/ asserted.
The agent setting this bit acted as the bus master for
the operation in which the error occurred.
The Parity Error Response bit in the
register is set.
fast
medium
slow
reserved
Command
[10:9]
[7:5]
[3:0]
11
8
4