LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 58

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.14 Chained Block Moves
2-34
1. Read
2. If the INTF bit is set, it must be written to a one to clear this status.
3. If only the SIP bit is set, read
4. If only the DIP bit is set, read the
5. If both the SIP and DIP bits are set, read
6. When using polled interrupts, go back to Step 1 before leaving the
Since the LSI53C875 has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the
Two (SCNTL2)
Chained Block Move instruction is illustrated in
Functional Description
SCSI Interrupt Status One (SIST1)
condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.
interrupt condition and get the DMA interrupt status. The bits in
DSTAT tell which DMA interrupts occurred and determine what
action is required to service the interrupts.
(SIST0),
(DSTAT)
interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the interrupt service routine. It is recommended that the DMA
interrupt be serviced before the SCSI interrupt, because a serious
DMA interrupt condition could influence how the SCSI interrupt is
acted upon.
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the IRQ/ pin is asserted again if there are any stacked interrupts.
This should cause the system to re-enter the interrupt service
routine.
Interrupt Status
to clear the SCSI and DMA interrupt condition and get the
SCSI Interrupt Status One
register are used to facilitate these situations. The
(ISTAT).
SCSI Interrupt Status Zero (SIST0)
DMA Status (DSTAT)
to clear the SCSI interrupt
(SIST1), and
SCSI Interrupt Status Zero
Figure
DMA Status
2.6.
SCSI Control
to clear the
and