LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 166

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-50
Register: 0x39 (0xB9)
DMA Interrupt Enable (DIEN)
Read/Write
R
MDPE
BF
ABRT
SSI
SIR
EBPE
IID
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
interrupt is masked by clearing the appropriate mask bit. Masking an
interrupt prevents IRQ/ from being asserted for the corresponding
interrupt, but the status bit is still set in the
Masking an interrupt does not prevent the ISTAT DIP from being set. All
DMA interrupts are considered fatal, therefore SCRIPTS stops running
when this condition occurs, whether or not the interrupt is masked.
Setting a mask bit enables the assertion of IRQ/ for the corresponding
interrupt. (A masked nonfatal interrupt does not prevent unmasked or
fatal interrupts from getting through; interrupt stacking begins when either
the ISTAT SIP or DIP bit is set.)
The IRQ/ output is latched. Once asserted, it will remain asserted until
the interrupt is cleared by reading the appropriate status register.
Masking an interrupt after the IRQ/ output is asserted does not cause
deassertion of IRQ/.
SCSI Operating Registers
R
7
x
MDPE
6
0
Reserved
Master Data Parity Error
Bus Fault
Aborted
Single-step Interrupt
SCRIPTS Interrupt Instruction Received
Extended Byte Parity Enable
(LSI53C875N only)
Illegal Instruction Detected
BF
5
0
ABRT
4
0
DMA Status (DSTAT)
SSI
3
0
DMA Status (DSTAT)
SIR
2
0
R
1
x
register. An
register.
IID
0
0
7
6
5
4
3
2
1
0