LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 131

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x05 (0x85)
SCSI Transfer (SXFER)
Read/Write
For additional information on how the synchronous transfer rate is
determined, refer to
TP[2:0]
7
0
Note:
Note:
TP[2:0]
0
When using Table Indirect I/O commands, bits [7:0] of this
register are loaded from the I/O data structure.
For Ultra SCSI transfers, the ideal transfer period is 4, and
5 is acceptable. Setting the transfer period to a value
greater than 5 is not recommended.
SCSI Synchronous Transfer Period
These bits determine the SCSI synchronous transfer
period used by the LSI53C875 when sending
synchronous SCSI data in either initiator or target mode.
These bits control the programmable dividers in the chip.
The synchronous transfer period the LSI53C875 should
use when transferring SCSI data is determined as in this
example.
TP2
0
0
0
0
1
1
1
1
Chapter 2, “Functional Description.”
5
0
TP1
0
0
1
1
0
0
1
1
4
0
TP0
0
1
0
1
0
1
0
1
0
MO[4:0]
XFERP
0
10
11
4
5
6
7
8
9
0
0
0
[7:5]
5-15