LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 187

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

SLT
ART
SOZ
SOM
Selection Response Logic Test
This bit is set when the LSI53C875 is ready to be
selected or reselected. This does not take into account
the bus settle delay of 400 ns. This bit is used for
functional test and fault purposes.
Arbitration Priority Encoder Test
This bit is always set when the LSI53C875 exhibits the
highest priority ID asserted on the SCSI bus during
arbitration. It is primarily used for chip level testing, but it
may be used during low level mode operation to
determine if the LSI53C875 has won arbitration.
SCSI Synchronous Offset Zero
This bit indicates that the current synchronous
SREQ/SACK offset is zero. This bit is not latched and
may change at any time. It is used in low level
synchronous SCSI operations. When this bit is set, the
LSI53C875, functioning as an initiator, is waiting for the
target to request data transfers. If the LSI53C875 is a
target, then the initiator has sent the offset number of
acknowledges.
SCSI Synchronous Offset Maximum
This bit indicates that the current synchronous
SREQ/SACK offset is the maximum specified by bits [3:0]
in the
latched and may change at any time. It is used in low
level synchronous SCSI operations. When this bit is set,
the LSI53C875, as a target, is waiting for the initiator to
acknowledge the data transfers. If the LSI53C875 is an
initiator, then the target has sent the offset number of
requests.
SCSI Transfer (SXFER)
register. This bit is not
5-71
3
2
1
0