LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 33

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.2 3.3 V/5 V PCI Interface
2.5.3 Additional Access to General Purpose Pins
The LSI53C875 can attach directly to a 3.3 V or a 5 V PCI interface, due
to separate V
be used on the universal board recommended by the PCI Special
Interest Group.
The LSI53C875 can access the GPIO0 and GPIO1 general purpose pins
through register bits in the PCI configuration space, instead of using the
General Purpose Pin Control (GPCNTL)
space to control these pins. In the LSI Logic SDMS software, the
configuration bits control pins as the clock and data lines, respectively.
To access the GPIO[1:0] pins through the configuration space, connect
a 4.7 k
internal pull-up that is sensed shortly after chip reset. If the pin is sensed
high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is
enabled. Additionally, if GPIO[1:0] access has been enabled through the
MAD[7] pin and if GPIO0 and/or GPIO1 are sensed low after chip reset,
GPIO[1:0] access is disabled. If GPIO[1:0] access through configuration
space is enabled, the GPIO0 and GPIO1 pins cannot be controlled from
the
(GPREG)
(GPREG)
Interface Control register at configuration addresses 0x34–0x35 controls
the GPIO0 and GPIO1 pins. For more information on GPIO[1:0] access,
refer to the Serial Interface Control register description in
Functional Description.”
Chapter 4, “Signal Descriptions.”
PCI Cache Mode
General Purpose Pin Control (GPCNTL)
Note:
resistor between the MAD[7] pin and V
registers, but are observable from the
register. When GPIO[1:0] access is enabled, the Serial
The LSI Logic SDMS software controls the GPIO0 and
GPIO1 pins using the
(GPCNTL)
Therefore, if using SDMS software, do not connect a 4.7 k
resistor between MAD[7] and Vss.
DD
pins for the PCI bus drivers. This allows the devices to
For more information on the GPIO pins, see
and
General Purpose (GPREG)
This does not apply to the LSI53C875E.
General Purpose Pin Control
register in the operating register
and
SS
General Purpose
General Purpose
. MAD[7] contains an
Chapter 3, “PCI
registers.
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