LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 214

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

6-18
Instruction Set of the I/O Processor
Data Structure Address (DSA)
offset relative to the value in the
(DSA)
SCSI ID, synchronous offset and synchronous period are
loaded from this address. Prior to the start of an I/O, load
the
of the I/O data structure. Any address on a longword
boundary is allowed. After a Table Indirect opcode is
fetched, the
the 24-bit signed offset value from the opcode to
generate the address of the required data. Both positive
and negative offsets are allowed. A subsequent fetch
from that address brings the data values into the chip.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O
operation. The I/O data structure can begin on any
longword boundary and may cross system segment
boundaries. There are two restrictions on the placement
of data in system memory:
Use this bit only in conjunction with the Select, Reselect,
Wait Select, and Wait Reselect instructions. Use bits 25
and 26 individually or in combination to produce the
following conditions:
Bit 25
The I/O data structure must lie within the 8 Mbytes
above or below the base address.
An I/O command structure must have all four bytes
contiguous in system memory, as shown below. The
offset/period bits are ordered as in the
(SXFER)
as in the
Data Structure Address (DSA)
Config
0
0
1
1
register. The
Bit 26
Data Structure Address (DSA)
SCSI Control Three (SCNTL3)
register. The configuration bits are ordered
0
1
0
1
SCSI Control Three (SCNTL3)
ID
Addressing Mode
Direct
Table Indirect
Relative
Table Relative
Offset/period
register, and used as an
Data Structure Address
with the base address
SCSI Transfer
is added to
register.
00
value,