LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 129

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

CCF[2:0]
Note:
It is important that these bits be set to the proper values to
guarantee that the LSI53C875 meets the SCSI timings as
defined by the ANSI specification.
at a time, with the least significant byte on SD[7:0]/, SDP/
and the most significant byte on SD[15:8]/, SDP1/.
Command, Status, and Message phases are not affected
by this bit.
Clearing this bit will also clear the Wide SCSI Receive bit
in the
indicates the presence of a valid data byte in the
Wide Residue (SWIDE)
Clock Conversion Factor
These bits select a factor by which the frequency of
SCLK is divided before being presented to the SCSI core.
The synchronous portion of the SCSI core can be run at
a different clock rate for fast SCSI, using the
Synchronous Clock Conversion Factor bits. The bit
encoding is displayed in the table below. All other
combinations are reserved and should never be used.
For additional information on how the synchronous
transfer rate is determined, refer to
tional Description.”
To migrate from a Fast SCSI-2 system with a 40 MHz
clock, divide the clock by a factor of two or more to
achieve the same synchronous transfer rate in a system
with an 80 MHz clock.
CCF2
SCF2
0
0
0
0
1
1
1
1
SCSI Control Two (SCNTL2)
SCF1
CCF1
0
0
1
1
0
0
1
1
SCF0
CCF0
0
1
0
1
0
1
0
1
register.
Frequency
SCLK/1.5
Reserved
Reserved
SCLK/3
SCLK/1
SCLK/2
SCLK/3
SCLK/4
Factor
register, which
Chapter 2, “Func-
75.01–80.00
SCSI Clock
50.01–75.0
16.67–25.0
25.01–37.5
37.51–50.0
50.01–75.0
(MHz)
–
–
SCSI
[2:0]
5-13