LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 310

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

reselected bit
reset SCSI offset bit
RESPID0 register
RESPID1 register
response ID one register
response ID zero register
revision level bits
S
SACK/ status bit
SATN/ active
SATN/ active bit
SATN/ status bit
SBCL register
SBDL register
SBR register
SBSY status bit
SC_D/ status bit
SCID register
SCLK bit
SCNTL0 register
SCNTL1 register
SCNTL2 register
SCNTL3 register
scratch register
scratchA register
scratchA/B operation bit
scratchB register
SCRIPTS bit
SCRIPTS interrupt instruction received bit
SCRIPTS processor
SCRIPTS RAM
SCSI
SCSI ATN condition - target mode
SCSI ATN condition bit
SCSI bus control lines register
SCSI bus data lines register
SCSI bus interface
IX-6
SODR most significant byte full
software reset
source I/O memory enable
SREQ/ status
SSEL/ status
start DMA operation
start SCSI transfer
start sequence
synchronous clock conversion factor
target mode
timer test mode
TolerANT enable
Ultra enable
unexpected disconnect
wide SCSI receive
wide SCSI send
won arbitration
write and invalidate enable
instruction prefetching
internal RAM for instruction storage
performance
scratchA/B operation bit
core
differential mode
termination
timings
TolerANT technology
2-1
5-72
7-51
5-51
5-62
5-57
5-54
5-14
5-22
5-78
2-23
5-51
2-3
5-6
5-22
5-12
5-57
2-2
5-22
5-23
5-22
5-3
5-6
5-9
5-12
5-22
5-47
5-79
5-37
5-22
5-69
5-70
,
5-32
5-4
5-27
2-19
5-76
5-57
5-10
2-2
5-73
2-20
5-75
5-11
5-8
5-54
5-52
5-36
to
5-70
1-5
5-69
2-5
5-55
Index
5-36
5-78
2-25
5-48
5-38
5-22
,
5-58
5-54
5-29
2-3
5-12
5-24
SCSI C_D/ signal bit
SCSI chip ID register
SCSI control enable bit
SCSI control one register
SCSI control three register
SCSI control two register
SCSI control zero register
SCSI core
SCSI data high impedance bit
SCSI destination ID register
SCSI differential mode bit
SCSI disconnect unexpected bit
SCSI FIFO test read bit
SCSI FIFO test write bit
SCSI first byte received register
SCSI gross error bit
SCSI high impedance mode bit
SCSI I_O/ signal bit
SCSI input data latch register
SCSI instructions
SCSI interrupt enable one register
SCSI interrupt enable zero register
SCSI interrupt pending bit
SCSI interrupt status one register
SCSI interrupt status zero register
SCSI isolation mode bits
SCSI longitudinal parity register
SCSI loopback mode bit
SCSI low level mode bit
SCSI MSG/ signal bit
SCSI output control latch register
SCSI output data latch register
SCSI parity error bit
SCSI phase mismatch bit
SCSI reset condition bit
SCSI RST/ received bit
SCSI RST/ signal bit
SCSI SCRIPTS operation
SCSI SDP0/ parity signal bit
SCSI SDP1 signal bit
SCSI selected as ID bits
SCSI selector ID register
SCSI status one register
SCSI status two register
SCSI status zero register
SCSI synchronous offset maximum
SCSI synchronous offset zero bit
SCSI test one register
SCSI test three register
SCSI test two register
SCSI test zero register
SCSI timer one register
SCSI timer zero register
SCSI timing diagrams
SCSI transfer register
SCSI true end of process bit
SCSI valid bit
SCSI wide residue register
SDID register
block move
I/O
load/store
memory move
read/write
transfer control
sample instruction
6-12
2-1
6-37
6-21
5-18
5-22
6-5
6-33
6-26
5-28
5-54
5-55
5-28
5-27
5-14
5-28
5-30
5-15
6-3
7-51
5-73
5-72
5-70
5-73
5-58
5-75
5-66
5-75
5-55
5-77
5-74
5-64
5-74
5-29
,
5-72
5-70
5-27
5-22
5-9
5-6
5-26
5-54
6-1
5-73
5-3
5-33
5-57
5-12
5-61
5-18
5-27
5-36
5-77
5-40
5-78
5-74
5-60
5-9
5-20
5-71
5-21
5-59
5-56
5-55
5-53
5-71