LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 39

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 2.4
2.5.8 DMA FIFO
Figure 2.1
Transfers
Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5,
PAR = Parity Error (bit 0,
Deep
134
DPH
0
0
1
1
.
. .
SCSI Parity Errors and Interrupts
DMA FIFO Sections
Byte Lane 3
8 Bits
PAR
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO
is illustrated in
the LSI53C8XX family, the DMA FIFO size may be set to 88 bytes by
setting the DMA FIFO Size bit, bit 5 in the
register.
PCI Cache Mode
0
1
0
1
SCSI Interrupt Enable One
Description
Halts when a parity error occurs in target or initiator mode and does
not generate an interrupt.
Halts when a parity error occurs in target mode and generates an
interrupt in the target or initiator mode.
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is not generated.
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is generated.
Figure
Byte Lane 2
8 Bits
2.1. To assure compatibility with older products in
32 Bytes Wide
SCSI Control One
(SIEN1).
Byte Lane 1
8 Bits
Chip Test Five (CTEST5)
(SCNTL1).
Byte Lane 0
8 Bits
2-15
.
. .