LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 152

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-36
SIGP
CIO
CM
SRTCH
TEOP
SCSI Operating Registers
Note:
Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a read-modify-write to
this register.
Signal Process
This bit is a copy of the SIGP bit in the
(ISTAT)
running SCRIPTS instruction. When this register is read,
the SIGP bit in the
cleared.
Configured as I/O
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space. Both bits 4 and 5 are set if the chip
is dual-mapped.
Configured as Memory
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space. Both bits 4 and 5
are set if the chip is dual-mapped.
SCRATCHA/B Operation
This bit controls the operation of the
(SCRATCHA)
registers. When it is set, SCRATCHB contains the RAM
base address value from the PCI configuration RAM
Base Address register. This is the base address for the
4 Kbyte internal RAM. In addition, the
(SCRATCHA)
based address of the chip operating registers. When this
bit is cleared, the
Scratch Register B (SCRATCHB)
normal operation.
SCSI True End of Process
This bit indicates the status of the LSI53C875’s internal
TEOP signal. The TEOP signal acknowledges the
completion of a transfer through the SCSI portion of the
LSI53C875. When this bit is set, TEOP is active. When
this bit is clear, TEOP is inactive.
register (bit 5). The SIGP bit is used to signal a
and
register displays the memory mapped
Scratch Register A (SCRATCHA)
Scratch Register B (SCRATCHB)
Interrupt Status (ISTAT)
registers return to
Scratch Register A
Scratch Register A
Interrupt Status
register is
and
6
5
4
3
2